diff options
author | Stepan Moskovchenko <stepanm@codeaurora.org> | 2010-11-12 22:30:00 -0500 |
---|---|---|
committer | Daniel Walker <dwalker@codeaurora.org> | 2010-11-30 19:12:00 -0500 |
commit | 33069739d1c2f03734d5b5b003593e9552d412c1 (patch) | |
tree | c2eac6eb6bb8c8cbae29d78d8d4b17f02e47662a /arch/arm/mach-msm | |
parent | 100832c9b6adb3d63407416931caeba3f3b9a777 (diff) |
msm: iommu: Miscellaneous code cleanup
Remove some unneeded assignments and messages, restructure
a failure path in iova_to_phys, and make __flush_iotlb
return int in preparation for adding IOMMU clock control.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r-- | arch/arm/mach-msm/iommu.c | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index a468ee309d65..f65101742a74 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c | |||
@@ -50,12 +50,12 @@ struct msm_priv { | |||
50 | struct list_head list_attached; | 50 | struct list_head list_attached; |
51 | }; | 51 | }; |
52 | 52 | ||
53 | static void __flush_iotlb(struct iommu_domain *domain) | 53 | static int __flush_iotlb(struct iommu_domain *domain) |
54 | { | 54 | { |
55 | struct msm_priv *priv = domain->priv; | 55 | struct msm_priv *priv = domain->priv; |
56 | struct msm_iommu_drvdata *iommu_drvdata; | 56 | struct msm_iommu_drvdata *iommu_drvdata; |
57 | struct msm_iommu_ctx_drvdata *ctx_drvdata; | 57 | struct msm_iommu_ctx_drvdata *ctx_drvdata; |
58 | 58 | int ret = 0; | |
59 | #ifndef CONFIG_IOMMU_PGTABLES_L2 | 59 | #ifndef CONFIG_IOMMU_PGTABLES_L2 |
60 | unsigned long *fl_table = priv->pgtable; | 60 | unsigned long *fl_table = priv->pgtable; |
61 | int i; | 61 | int i; |
@@ -79,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain) | |||
79 | iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); | 79 | iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); |
80 | SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); | 80 | SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); |
81 | } | 81 | } |
82 | |||
83 | return ret; | ||
82 | } | 84 | } |
83 | 85 | ||
84 | static void __reset_context(void __iomem *base, int ctx) | 86 | static void __reset_context(void __iomem *base, int ctx) |
@@ -267,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |||
267 | __pa(priv->pgtable)); | 269 | __pa(priv->pgtable)); |
268 | 270 | ||
269 | list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); | 271 | list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); |
270 | __flush_iotlb(domain); | 272 | ret = __flush_iotlb(domain); |
271 | 273 | ||
272 | fail: | 274 | fail: |
273 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 275 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
@@ -282,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, | |||
282 | struct msm_iommu_drvdata *iommu_drvdata; | 284 | struct msm_iommu_drvdata *iommu_drvdata; |
283 | struct msm_iommu_ctx_drvdata *ctx_drvdata; | 285 | struct msm_iommu_ctx_drvdata *ctx_drvdata; |
284 | unsigned long flags; | 286 | unsigned long flags; |
287 | int ret; | ||
285 | 288 | ||
286 | spin_lock_irqsave(&msm_iommu_lock, flags); | 289 | spin_lock_irqsave(&msm_iommu_lock, flags); |
287 | priv = domain->priv; | 290 | priv = domain->priv; |
@@ -296,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, | |||
296 | if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) | 299 | if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) |
297 | goto fail; | 300 | goto fail; |
298 | 301 | ||
299 | __flush_iotlb(domain); | 302 | ret = __flush_iotlb(domain); |
303 | if (ret) | ||
304 | goto fail; | ||
305 | |||
300 | __reset_context(iommu_drvdata->base, ctx_dev->num); | 306 | __reset_context(iommu_drvdata->base, ctx_dev->num); |
301 | list_del_init(&ctx_drvdata->attached_elm); | 307 | list_del_init(&ctx_drvdata->attached_elm); |
302 | 308 | ||
@@ -410,7 +416,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
410 | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; | 416 | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; |
411 | } | 417 | } |
412 | 418 | ||
413 | __flush_iotlb(domain); | 419 | ret = __flush_iotlb(domain); |
414 | fail: | 420 | fail: |
415 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 421 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
416 | return ret; | 422 | return ret; |
@@ -495,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va, | |||
495 | } | 501 | } |
496 | } | 502 | } |
497 | 503 | ||
498 | __flush_iotlb(domain); | 504 | ret = __flush_iotlb(domain); |
499 | fail: | 505 | fail: |
500 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 506 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
501 | return ret; | 507 | return ret; |
@@ -530,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, | |||
530 | SET_CTX_TLBIALL(base, ctx, 0); | 536 | SET_CTX_TLBIALL(base, ctx, 0); |
531 | SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); | 537 | SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); |
532 | 538 | ||
533 | if (GET_FAULT(base, ctx)) | ||
534 | goto fail; | ||
535 | |||
536 | par = GET_PAR(base, ctx); | 539 | par = GET_PAR(base, ctx); |
537 | 540 | ||
538 | /* We are dealing with a supersection */ | 541 | /* We are dealing with a supersection */ |
@@ -541,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, | |||
541 | else /* Upper 20 bits from PAR, lower 12 from VA */ | 544 | else /* Upper 20 bits from PAR, lower 12 from VA */ |
542 | ret = (par & 0xFFFFF000) | (va & 0x00000FFF); | 545 | ret = (par & 0xFFFFF000) | (va & 0x00000FFF); |
543 | 546 | ||
547 | if (GET_FAULT(base, ctx)) | ||
548 | ret = 0; | ||
549 | |||
544 | fail: | 550 | fail: |
545 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 551 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
546 | return ret; | 552 | return ret; |
@@ -583,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
583 | { | 589 | { |
584 | struct msm_iommu_drvdata *drvdata = dev_id; | 590 | struct msm_iommu_drvdata *drvdata = dev_id; |
585 | void __iomem *base; | 591 | void __iomem *base; |
586 | unsigned int fsr = 0; | 592 | unsigned int fsr; |
587 | int ncb = 0, i = 0; | 593 | int ncb, i; |
588 | 594 | ||
589 | spin_lock(&msm_iommu_lock); | 595 | spin_lock(&msm_iommu_lock); |
590 | 596 | ||
@@ -595,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
595 | 601 | ||
596 | base = drvdata->base; | 602 | base = drvdata->base; |
597 | 603 | ||
598 | pr_err("===== WOAH! =====\n"); | ||
599 | pr_err("Unexpected IOMMU page fault!\n"); | 604 | pr_err("Unexpected IOMMU page fault!\n"); |
600 | pr_err("base = %08x\n", (unsigned int) base); | 605 | pr_err("base = %08x\n", (unsigned int) base); |
601 | 606 | ||