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authorMarc Zyngier <marc.zyngier@arm.com>2011-09-08 08:15:22 -0400
committerArnd Bergmann <arnd@arndb.de>2012-09-14 05:14:57 -0400
commit44ea349f5b7e0b4865de9ca6b4437c746eede40c (patch)
treefc6b41a24bc610dc7afedc3117fd84a6f3b6b2fa /arch/arm/mach-msm/platsmp.c
parent06853ae475e1386d6d11d139ba7bf2c97b3d1768 (diff)
ARM: SoC: convert MSM to SMP operations
Convert MSM SMP platforms to use struct smp_operations to provide their SMP and CPU hotplug operations. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: David Brown <davidb@codeaurora.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-msm/platsmp.c')
-rw-r--r--arch/arm/mach-msm/platsmp.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index e012dc8391cf..ba3c4b0d523d 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -25,6 +25,7 @@
25#include <mach/msm_iomap.h> 25#include <mach/msm_iomap.h>
26 26
27#include "scm-boot.h" 27#include "scm-boot.h"
28#include "core.h"
28 29
29#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 30#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
30#define SCSS_CPU1CORE_RESET 0xD80 31#define SCSS_CPU1CORE_RESET 0xD80
@@ -48,7 +49,7 @@ static inline int get_core_count(void)
48 return ((read_cpuid_id() >> 4) & 3) + 1; 49 return ((read_cpuid_id() >> 4) & 3) + 1;
49} 50}
50 51
51void __cpuinit platform_secondary_init(unsigned int cpu) 52static void __cpuinit msm_secondary_init(unsigned int cpu)
52{ 53{
53 /* Configure edge-triggered PPIs */ 54 /* Configure edge-triggered PPIs */
54 writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); 55 writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@@ -93,7 +94,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
93 "address\n"); 94 "address\n");
94} 95}
95 96
96int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 97static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
97{ 98{
98 unsigned long timeout; 99 unsigned long timeout;
99 static int cold_boot_done; 100 static int cold_boot_done;
@@ -153,7 +154,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
153 * does not support the ARM SCU, so just set the possible cpu mask to 154 * does not support the ARM SCU, so just set the possible cpu mask to
154 * NR_CPUS. 155 * NR_CPUS.
155 */ 156 */
156void __init smp_init_cpus(void) 157static void __init msm_smp_init_cpus(void)
157{ 158{
158 unsigned int i, ncores = get_core_count(); 159 unsigned int i, ncores = get_core_count();
159 160
@@ -169,6 +170,16 @@ void __init smp_init_cpus(void)
169 set_smp_cross_call(gic_raise_softirq); 170 set_smp_cross_call(gic_raise_softirq);
170} 171}
171 172
172void __init platform_smp_prepare_cpus(unsigned int max_cpus) 173static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
173{ 174{
174} 175}
176
177struct smp_operations msm_smp_ops __initdata = {
178 .smp_init_cpus = msm_smp_init_cpus,
179 .smp_prepare_cpus = msm_smp_prepare_cpus,
180 .smp_secondary_init = msm_secondary_init,
181 .smp_boot_secondary = msm_boot_secondary,
182#ifdef CONFIG_HOTPLUG_CPU
183 .cpu_die = msm_cpu_die,
184#endif
185};