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authorJeff Ohlstein <johlstei@codeaurora.org>2011-04-07 20:41:09 -0400
committerArnd Bergmann <arnd@arndb.de>2011-07-21 10:43:03 -0400
commit41ff445cdb8b3d618425f8a16e2b873046bbe536 (patch)
tree60a660c1f1924b23185f67b21869b964f57e164a /arch/arm/mach-msm/platsmp.c
parent620917de59eeb934b9f8cf35cc2d95c1ac8ed0fc (diff)
ARM: msm: platsmp: determine number of CPU cores at boot time
Previously we just assumed there were CONFIG_NR_CPUS cpus present in the system. Instead, figure out the number of cpus from the MIDR register. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> [arnd: clarified patch title] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-msm/platsmp.c')
-rw-r--r--arch/arm/mach-msm/platsmp.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 2034098cf015..5ba77d00361c 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -18,6 +18,7 @@
18 18
19#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/cputype.h>
21#include <asm/mach-types.h> 22#include <asm/mach-types.h>
22 23
23#include <mach/msm_iomap.h> 24#include <mach/msm_iomap.h>
@@ -40,6 +41,12 @@ volatile int pen_release = -1;
40 41
41static DEFINE_SPINLOCK(boot_lock); 42static DEFINE_SPINLOCK(boot_lock);
42 43
44static inline int get_core_count(void)
45{
46 /* 1 + the PART[1:0] field of MIDR */
47 return ((read_cpuid_id() >> 4) & 3) + 1;
48}
49
43void __cpuinit platform_secondary_init(unsigned int cpu) 50void __cpuinit platform_secondary_init(unsigned int cpu)
44{ 51{
45 /* Configure edge-triggered PPIs */ 52 /* Configure edge-triggered PPIs */
@@ -147,9 +154,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
147 */ 154 */
148void __init smp_init_cpus(void) 155void __init smp_init_cpus(void)
149{ 156{
150 unsigned int i; 157 unsigned int i, ncores = get_core_count();
151 158
152 for (i = 0; i < NR_CPUS; i++) 159 for (i = 0; i < ncores; i++)
153 set_cpu_possible(i, true); 160 set_cpu_possible(i, true);
154 161
155 set_smp_cross_call(gic_raise_softirq); 162 set_smp_cross_call(gic_raise_softirq);