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authorStephen Boyd <sboyd@codeaurora.org>2015-03-13 14:09:34 -0400
committerKumar Gala <galak@codeaurora.org>2015-03-27 12:31:02 -0400
commitc0c89fafa289ea241ba3fb22d6f583f8089a719e (patch)
tree43e48055d1330a7fece805554b87f372d63e718d /arch/arm/mach-msm/include/mach
parent9eccca0843205f87c00404b663188b88eb248051 (diff)
ARM: Remove mach-msm and associated ARM architecture code
The maintainers for mach-msm no longer have any plans to support or test the platforms supported by this architecture[1]. Most likely there aren't any active users of this code anyway, so let's delete it. [1] http://lkml.kernel.org/r/20150307031212.GA8434@fifo99.com Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include/mach')
-rw-r--r--arch/arm/mach-msm/include/mach/clk.h31
-rw-r--r--arch/arm/mach-msm/include/mach/dma.h151
-rw-r--r--arch/arm/mach-msm/include/mach/entry-macro.S36
-rw-r--r--arch/arm/mach-msm/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x00.h75
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x30.h153
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8x50.h88
-rw-r--r--arch/arm/mach-msm/include/mach/irqs.h37
-rw-r--r--arch/arm/mach-msm/include/mach/msm_gpiomux.h38
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h108
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h103
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h125
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h53
-rw-r--r--arch/arm/mach-msm/include/mach/msm_smd.h109
-rw-r--r--arch/arm/mach-msm/include/mach/sirc.h98
-rw-r--r--arch/arm/mach-msm/include/mach/vreg.h29
16 files changed, 0 insertions, 1252 deletions
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
deleted file mode 100644
index fd4f4a7a83b3..000000000000
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MACH_CLK_H
13#define __MACH_CLK_H
14
15/* Magic rate value for use with PM QOS to request the board's maximum
16 * supported AXI rate. PM QOS will only pass positive s32 rate values
17 * through to the clock driver, so INT_MAX is used.
18 */
19#define MSM_AXI_MAX_FREQ LONG_MAX
20
21enum clk_reset_action {
22 CLK_RESET_DEASSERT = 0,
23 CLK_RESET_ASSERT = 1
24};
25
26struct clk;
27
28/* Assert/Deassert reset to a hardware block associated with a clock */
29int clk_reset(struct clk *clk, enum clk_reset_action action);
30
31#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
deleted file mode 100644
index a72d48d42342..000000000000
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/* linux/include/asm-arm/arch-msm/dma.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_DMA_H
17
18#include <linux/list.h>
19
20struct msm_dmov_errdata {
21 uint32_t flush[6];
22};
23
24struct msm_dmov_cmd {
25 struct list_head list;
26 unsigned int cmdptr;
27 void (*complete_func)(struct msm_dmov_cmd *cmd,
28 unsigned int result,
29 struct msm_dmov_errdata *err);
30 void (*execute_func)(struct msm_dmov_cmd *cmd);
31 void *data;
32};
33
34#ifndef CONFIG_ARCH_MSM8X60
35void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
36void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
37int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
38#else
39static inline
40void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
41static inline
42void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
43static inline
44int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
45#endif
46
47#define DMOV_CMD_LIST (0 << 29) /* does not work */
48#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
49#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
50#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
51#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
52
53#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
54#define DMOV_RSLT_ERROR (1 << 3)
55#define DMOV_RSLT_FLUSH (1 << 2)
56#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
57#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
58
59#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
60#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
61#define DMOV_STATUS_RSLT_VALID (1 << 1)
62#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
63
64#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
65#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
66#define DMOV_CONFIG_IRQ_EN (1 << 0)
67
68/* channel assignments */
69
70#define DMOV_NAND_CHAN 7
71#define DMOV_NAND_CRCI_CMD 5
72#define DMOV_NAND_CRCI_DATA 4
73
74#define DMOV_SDC1_CHAN 8
75#define DMOV_SDC1_CRCI 6
76
77#define DMOV_SDC2_CHAN 8
78#define DMOV_SDC2_CRCI 7
79
80#define DMOV_TSIF_CHAN 10
81#define DMOV_TSIF_CRCI 10
82
83#define DMOV_USB_CHAN 11
84
85/* no client rate control ifc (eg, ram) */
86#define DMOV_NONE_CRCI 0
87
88
89/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
90 * is going to walk a list of 32bit pointers as described below. Each
91 * pointer points to a *array* of dmov_s, etc structs. The last pointer
92 * in the list is marked with CMD_PTR_LP. The last struct in each array
93 * is marked with CMD_LC (see below).
94 */
95#define CMD_PTR_ADDR(addr) ((addr) >> 3)
96#define CMD_PTR_LP (1 << 31) /* last pointer */
97#define CMD_PTR_PT (3 << 29) /* ? */
98
99/* Single Item Mode */
100typedef struct {
101 unsigned cmd;
102 unsigned src;
103 unsigned dst;
104 unsigned len;
105} dmov_s;
106
107/* Scatter/Gather Mode */
108typedef struct {
109 unsigned cmd;
110 unsigned src_dscr;
111 unsigned dst_dscr;
112 unsigned _reserved;
113} dmov_sg;
114
115/* Box mode */
116typedef struct {
117 uint32_t cmd;
118 uint32_t src_row_addr;
119 uint32_t dst_row_addr;
120 uint32_t src_dst_len;
121 uint32_t num_rows;
122 uint32_t row_offset;
123} dmov_box;
124
125/* bits for the cmd field of the above structures */
126
127#define CMD_LC (1 << 31) /* last command */
128#define CMD_FR (1 << 22) /* force result -- does not work? */
129#define CMD_OCU (1 << 21) /* other channel unblock */
130#define CMD_OCB (1 << 20) /* other channel block */
131#define CMD_TCB (1 << 19) /* ? */
132#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
133#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
134
135#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
136#define CMD_MODE_SG (1 << 0) /* untested */
137#define CMD_MODE_IND_SG (2 << 0) /* untested */
138#define CMD_MODE_BOX (3 << 0) /* untested */
139
140#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
141#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
142#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
143
144#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
145#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
146#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
147
148#define CMD_DST_CRCI(n) (((n) & 15) << 7)
149#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
150
151#endif
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
deleted file mode 100644
index f2ae9087f654..000000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ /dev/null
@@ -1,36 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#if !defined(CONFIG_ARM_GIC)
20#include <mach/msm_iomap.h>
21
22 .macro get_irqnr_preamble, base, tmp
23 @ enable imprecise aborts
24 cpsie a
25 mov \base, #MSM_VIC_BASE
26 .endm
27
28 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
29 @ 0xD0 has irq# or old irq# if the irq has been handled
30 @ 0xD4 has irq# or -1 if none pending *but* if you just
31 @ read 0xD4 you never get the first irq for some reason
32 ldr \irqnr, [\base, #0xD0]
33 ldr \irqnr, [\base, #0xD4]
34 cmp \irqnr, #0xffffffff
35 .endm
36#endif
diff --git a/arch/arm/mach-msm/include/mach/hardware.h b/arch/arm/mach-msm/include/mach/hardware.h
deleted file mode 100644
index 2d126091ae41..000000000000
--- a/arch/arm/mach-msm/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-msm/include/mach/hardware.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_HARDWARE_H
17
18#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x00.h b/arch/arm/mach-msm/include/mach/irqs-7x00.h
deleted file mode 100644
index f1fe70612fe9..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-7x00.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 */
6
7#ifndef __ASM_ARCH_MSM_IRQS_7X00_H
8#define __ASM_ARCH_MSM_IRQS_7X00_H
9
10/* MSM ARM11 Interrupt Numbers */
11/* See 80-VE113-1 A, pp219-221 */
12
13#define INT_A9_M2A_0 0
14#define INT_A9_M2A_1 1
15#define INT_A9_M2A_2 2
16#define INT_A9_M2A_3 3
17#define INT_A9_M2A_4 4
18#define INT_A9_M2A_5 5
19#define INT_A9_M2A_6 6
20#define INT_GP_TIMER_EXP 7
21#define INT_DEBUG_TIMER_EXP 8
22#define INT_UART1 9
23#define INT_UART2 10
24#define INT_UART3 11
25#define INT_UART1_RX 12
26#define INT_UART2_RX 13
27#define INT_UART3_RX 14
28#define INT_USB_OTG 15
29#define INT_MDDI_PRI 16
30#define INT_MDDI_EXT 17
31#define INT_MDDI_CLIENT 18
32#define INT_MDP 19
33#define INT_GRAPHICS 20
34#define INT_ADM_AARM 21
35#define INT_ADSP_A11 22
36#define INT_ADSP_A9_A11 23
37#define INT_SDC1_0 24
38#define INT_SDC1_1 25
39#define INT_SDC2_0 26
40#define INT_SDC2_1 27
41#define INT_KEYSENSE 28
42#define INT_TCHSCRN_SSBI 29
43#define INT_TCHSCRN1 30
44#define INT_TCHSCRN2 31
45
46#define INT_GPIO_GROUP1 (32 + 0)
47#define INT_GPIO_GROUP2 (32 + 1)
48#define INT_PWB_I2C (32 + 2)
49#define INT_SOFTRESET (32 + 3)
50#define INT_NAND_WR_ER_DONE (32 + 4)
51#define INT_NAND_OP_DONE (32 + 5)
52#define INT_PBUS_ARM11 (32 + 6)
53#define INT_AXI_MPU_SMI (32 + 7)
54#define INT_AXI_MPU_EBI1 (32 + 8)
55#define INT_AD_HSSD (32 + 9)
56#define INT_ARM11_PMU (32 + 10)
57#define INT_ARM11_DMA (32 + 11)
58#define INT_TSIF_IRQ (32 + 12)
59#define INT_UART1DM_IRQ (32 + 13)
60#define INT_UART1DM_RX (32 + 14)
61#define INT_USB_HS (32 + 15)
62#define INT_SDC3_0 (32 + 16)
63#define INT_SDC3_1 (32 + 17)
64#define INT_SDC4_0 (32 + 18)
65#define INT_SDC4_1 (32 + 19)
66#define INT_UART2DM_RX (32 + 20)
67#define INT_UART2DM_IRQ (32 + 21)
68
69/* 22-31 are reserved */
70
71#define NR_MSM_IRQS 64
72#define NR_GPIO_IRQS 122
73#define NR_BOARD_IRQS 64
74
75#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h
deleted file mode 100644
index 1f15902655fd..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-7x30.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
14#define __ASM_ARCH_MSM_IRQS_7X30_H
15
16/* MSM ACPU Interrupt Numbers */
17
18#define INT_DEBUG_TIMER_EXP 0
19#define INT_GPT0_TIMER_EXP 1
20#define INT_GPT1_TIMER_EXP 2
21#define INT_WDT0_ACCSCSSBARK 3
22#define INT_WDT1_ACCSCSSBARK 4
23#define INT_AVS_SVIC 5
24#define INT_AVS_SVIC_SW_DONE 6
25#define INT_SC_DBG_RX_FULL 7
26#define INT_SC_DBG_TX_EMPTY 8
27#define INT_ARM11_PM 9
28#define INT_AVS_REQ_DOWN 10
29#define INT_AVS_REQ_UP 11
30#define INT_SC_ACG 12
31/* SCSS_VICFIQSTS0[13:15] are RESERVED */
32#define INT_L2_SVICCPUIRPTREQ 16
33#define INT_L2_SVICDMANSIRPTREQ 17
34#define INT_L2_SVICDMASIRPTREQ 18
35#define INT_L2_SVICSLVIRPTREQ 19
36#define INT_AD5A_MPROC_APPS_0 20
37#define INT_AD5A_MPROC_APPS_1 21
38#define INT_A9_M2A_0 22
39#define INT_A9_M2A_1 23
40#define INT_A9_M2A_2 24
41#define INT_A9_M2A_3 25
42#define INT_A9_M2A_4 26
43#define INT_A9_M2A_5 27
44#define INT_A9_M2A_6 28
45#define INT_A9_M2A_7 29
46#define INT_A9_M2A_8 30
47#define INT_A9_M2A_9 31
48
49#define INT_AXI_EBI1_SC (32 + 0)
50#define INT_IMEM_ERR (32 + 1)
51#define INT_AXI_EBI0_SC (32 + 2)
52#define INT_PBUS_SC_IRQC (32 + 3)
53#define INT_PERPH_BUS_BPM (32 + 4)
54#define INT_CC_TEMP_SENSE (32 + 5)
55#define INT_UXMC_EBI0 (32 + 6)
56#define INT_UXMC_EBI1 (32 + 7)
57#define INT_EBI2_OP_DONE (32 + 8)
58#define INT_EBI2_WR_ER_DONE (32 + 9)
59#define INT_TCSR_SPSS_CE (32 + 10)
60#define INT_EMDH (32 + 11)
61#define INT_PMDH (32 + 12)
62#define INT_MDC (32 + 13)
63#define INT_MIDI_TO_SUPSS (32 + 14)
64#define INT_LPA_2 (32 + 15)
65#define INT_GPIO_GROUP1_SECURE (32 + 16)
66#define INT_GPIO_GROUP2_SECURE (32 + 17)
67#define INT_GPIO_GROUP1 (32 + 18)
68#define INT_GPIO_GROUP2 (32 + 19)
69#define INT_MPRPH_SOFTRESET (32 + 20)
70#define INT_PWB_I2C (32 + 21)
71#define INT_PWB_I2C_2 (32 + 22)
72#define INT_TSSC_SAMPLE (32 + 23)
73#define INT_TSSC_PENUP (32 + 24)
74#define INT_TCHSCRN_SSBI (32 + 25)
75#define INT_FM_RDS (32 + 26)
76#define INT_KEYSENSE (32 + 27)
77#define INT_USB_OTG_HS (32 + 28)
78#define INT_USB_OTG_HS2 (32 + 29)
79#define INT_USB_OTG_HS3 (32 + 30)
80#define INT_CSI (32 + 31)
81
82#define INT_SPI_OUTPUT (64 + 0)
83#define INT_SPI_INPUT (64 + 1)
84#define INT_SPI_ERROR (64 + 2)
85#define INT_UART1 (64 + 3)
86#define INT_UART1_RX (64 + 4)
87#define INT_UART2 (64 + 5)
88#define INT_UART2_RX (64 + 6)
89#define INT_UART3 (64 + 7)
90#define INT_UART3_RX (64 + 8)
91#define INT_UART1DM_IRQ (64 + 9)
92#define INT_UART1DM_RX (64 + 10)
93#define INT_UART2DM_IRQ (64 + 11)
94#define INT_UART2DM_RX (64 + 12)
95#define INT_TSIF (64 + 13)
96#define INT_ADM_SC1 (64 + 14)
97#define INT_ADM_SC2 (64 + 15)
98#define INT_MDP (64 + 16)
99#define INT_VPE (64 + 17)
100#define INT_GRP_2D (64 + 18)
101#define INT_GRP_3D (64 + 19)
102#define INT_ROTATOR (64 + 20)
103#define INT_MFC720 (64 + 21)
104#define INT_JPEG (64 + 22)
105#define INT_VFE (64 + 23)
106#define INT_TV_ENC (64 + 24)
107#define INT_PMIC_SSBI (64 + 25)
108#define INT_MPM_1 (64 + 26)
109#define INT_TCSR_SPSS_SAMPLE (64 + 27)
110#define INT_TCSR_SPSS_PENUP (64 + 28)
111#define INT_MPM_2 (64 + 29)
112#define INT_SDC1_0 (64 + 30)
113#define INT_SDC1_1 (64 + 31)
114
115#define INT_SDC3_0 (96 + 0)
116#define INT_SDC3_1 (96 + 1)
117#define INT_SDC2_0 (96 + 2)
118#define INT_SDC2_1 (96 + 3)
119#define INT_SDC4_0 (96 + 4)
120#define INT_SDC4_1 (96 + 5)
121#define INT_PWB_QUP_IN (96 + 6)
122#define INT_PWB_QUP_OUT (96 + 7)
123#define INT_PWB_QUP_ERR (96 + 8)
124#define INT_SCSS_WDT0_BITE (96 + 9)
125/* SCSS_VICFIQSTS3[10:31] are RESERVED */
126
127/* Retrofit universal macro names */
128#define INT_ADM_AARM INT_ADM_SC2
129#define INT_USB_HS INT_USB_OTG_HS
130#define INT_USB_OTG INT_USB_OTG_HS
131#define INT_TCHSCRN1 INT_TSSC_SAMPLE
132#define INT_TCHSCRN2 INT_TSSC_PENUP
133#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP
134#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0
135#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1
136#define INT_MDDI_EXT INT_EMDH
137#define INT_MDDI_PRI INT_PMDH
138#define INT_MDDI_CLIENT INT_MDC
139#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE
140#define INT_NAND_OP_DONE INT_EBI2_OP_DONE
141
142#define NR_MSM_IRQS 128
143#define NR_GPIO_IRQS 182
144#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
145#define NR_PMIC8058_GPIO_IRQS 40
146#define NR_PMIC8058_MPP_IRQS 12
147#define NR_PMIC8058_MISC_IRQS 8
148#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\
149 NR_PMIC8058_MPP_IRQS +\
150 NR_PMIC8058_MISC_IRQS)
151#define NR_BOARD_IRQS NR_PMIC8058_IRQS
152
153#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h
deleted file mode 100644
index 26adbe0e9406..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-8x50.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
14#define __ASM_ARCH_MSM_IRQS_8XXX_H
15
16/* MSM ACPU Interrupt Numbers */
17
18#define INT_A9_M2A_0 0
19#define INT_A9_M2A_1 1
20#define INT_A9_M2A_2 2
21#define INT_A9_M2A_3 3
22#define INT_A9_M2A_4 4
23#define INT_A9_M2A_5 5
24#define INT_A9_M2A_6 6
25#define INT_GP_TIMER_EXP 7
26#define INT_DEBUG_TIMER_EXP 8
27#define INT_SIRC_0 9
28#define INT_SDC3_0 10
29#define INT_SDC3_1 11
30#define INT_SDC4_0 12
31#define INT_SDC4_1 13
32#define INT_AD6_EXT_VFR 14
33#define INT_USB_OTG 15
34#define INT_MDDI_PRI 16
35#define INT_MDDI_EXT 17
36#define INT_MDDI_CLIENT 18
37#define INT_MDP 19
38#define INT_GRAPHICS 20
39#define INT_ADM_AARM 21
40#define INT_ADSP_A11 22
41#define INT_ADSP_A9_A11 23
42#define INT_SDC1_0 24
43#define INT_SDC1_1 25
44#define INT_SDC2_0 26
45#define INT_SDC2_1 27
46#define INT_KEYSENSE 28
47#define INT_TCHSCRN_SSBI 29
48#define INT_TCHSCRN1 30
49#define INT_TCHSCRN2 31
50
51#define INT_TCSR_MPRPH_SC1 (32 + 0)
52#define INT_USB_FS2 (32 + 1)
53#define INT_PWB_I2C (32 + 2)
54#define INT_SOFTRESET (32 + 3)
55#define INT_NAND_WR_ER_DONE (32 + 4)
56#define INT_NAND_OP_DONE (32 + 5)
57#define INT_TCSR_MPRPH_SC2 (32 + 6)
58#define INT_OP_PEN (32 + 7)
59#define INT_AD_HSSD (32 + 8)
60#define INT_ARM11_PM (32 + 9)
61#define INT_SDMA_NON_SECURE (32 + 10)
62#define INT_TSIF_IRQ (32 + 11)
63#define INT_UART1DM_IRQ (32 + 12)
64#define INT_UART1DM_RX (32 + 13)
65#define INT_SDMA_SECURE (32 + 14)
66#define INT_SI2S_SLAVE (32 + 15)
67#define INT_SC_I2CPU (32 + 16)
68#define INT_SC_DBG_RDTRFULL (32 + 17)
69#define INT_SC_DBG_WDTRFULL (32 + 18)
70#define INT_SCPLL_CTL_DONE (32 + 19)
71#define INT_UART2DM_IRQ (32 + 20)
72#define INT_UART2DM_RX (32 + 21)
73#define INT_VDC_MEC (32 + 22)
74#define INT_VDC_DB (32 + 23)
75#define INT_VDC_AXI (32 + 24)
76#define INT_VFE (32 + 25)
77#define INT_USB_HS (32 + 26)
78#define INT_AUDIO_OUT0 (32 + 27)
79#define INT_AUDIO_OUT1 (32 + 28)
80#define INT_CRYPTO (32 + 29)
81#define INT_AD6M_IDLE (32 + 30)
82#define INT_SIRC_1 (32 + 31)
83
84#define NR_GPIO_IRQS 165
85#define NR_MSM_IRQS 64
86#define NR_BOARD_IRQS 64
87
88#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
deleted file mode 100644
index 164d355c96ea..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_IRQS_H
18#define __ASM_ARCH_MSM_IRQS_H
19
20#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
21
22#if defined(CONFIG_ARCH_MSM7X30)
23#include "irqs-7x30.h"
24#elif defined(CONFIG_ARCH_QSD8X50)
25#include "irqs-8x50.h"
26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM_ARM11)
28#include "irqs-7x00.h"
29#else
30#error "Unknown architecture specification"
31#endif
32
33#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
34#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
35#define MSM_INT_TO_REG(base, irq) (base + irq / 32)
36
37#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_gpiomux.h b/arch/arm/mach-msm/include/mach/msm_gpiomux.h
deleted file mode 100644
index 0c7d3936e02f..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_gpiomux.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _LINUX_MSM_GPIOMUX_H
14#define _LINUX_MSM_GPIOMUX_H
15
16#ifdef CONFIG_MSM_GPIOMUX
17
18/* Increment a gpio's reference count, possibly activating the line. */
19int __must_check msm_gpiomux_get(unsigned gpio);
20
21/* Decrement a gpio's reference count, possibly suspending the line. */
22int msm_gpiomux_put(unsigned gpio);
23
24#else
25
26static inline int __must_check msm_gpiomux_get(unsigned gpio)
27{
28 return -ENOSYS;
29}
30
31static inline int msm_gpiomux_put(unsigned gpio)
32{
33 return -ENOSYS;
34}
35
36#endif
37
38#endif /* _LINUX_MSM_GPIOMUX_H */
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
deleted file mode 100644
index 67dc0e98b958..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/* arch/arm/mach-msm/include/mach/msm_iomap.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * The MSM peripherals are spread all over across 768MB of physical
18 * space, which makes just having a simple IO_ADDRESS macro to slide
19 * them into the right virtual location rough. Instead, we will
20 * provide a master phys->virt mapping for peripherals here.
21 *
22 */
23
24#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
25#define __ASM_ARCH_MSM_IOMAP_7X00_H
26
27#include <asm/sizes.h>
28
29/* Physical base address and size of peripherals.
30 * Ordered by the virtual base addresses they will be mapped at.
31 *
32 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
33 * instruction, otherwise entry-macro.S will not compile.
34 *
35 * If you add or remove entries here, you'll want to edit the
36 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
37 * changes.
38 *
39 */
40
41#define MSM_VIC_BASE IOMEM(0xE0000000)
42#define MSM_VIC_PHYS 0xC0000000
43#define MSM_VIC_SIZE SZ_4K
44
45#define MSM7X00_CSR_PHYS 0xC0100000
46#define MSM7X00_CSR_SIZE SZ_4K
47
48#define MSM_DMOV_BASE IOMEM(0xE0002000)
49#define MSM_DMOV_PHYS 0xA9700000
50#define MSM_DMOV_SIZE SZ_4K
51
52#define MSM7X00_GPIO1_PHYS 0xA9200000
53#define MSM7X00_GPIO1_SIZE SZ_4K
54
55#define MSM7X00_GPIO2_PHYS 0xA9300000
56#define MSM7X00_GPIO2_SIZE SZ_4K
57
58#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
59#define MSM_CLK_CTL_PHYS 0xA8600000
60#define MSM_CLK_CTL_SIZE SZ_4K
61
62#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
63#define MSM_SHARED_RAM_PHYS 0x01F00000
64#define MSM_SHARED_RAM_SIZE SZ_1M
65
66#define MSM_UART1_PHYS 0xA9A00000
67#define MSM_UART1_SIZE SZ_4K
68
69#define MSM_UART2_PHYS 0xA9B00000
70#define MSM_UART2_SIZE SZ_4K
71
72#define MSM_UART3_PHYS 0xA9C00000
73#define MSM_UART3_SIZE SZ_4K
74
75#define MSM_SDC1_PHYS 0xA0400000
76#define MSM_SDC1_SIZE SZ_4K
77
78#define MSM_SDC2_PHYS 0xA0500000
79#define MSM_SDC2_SIZE SZ_4K
80
81#define MSM_SDC3_PHYS 0xA0600000
82#define MSM_SDC3_SIZE SZ_4K
83
84#define MSM_SDC4_PHYS 0xA0700000
85#define MSM_SDC4_SIZE SZ_4K
86
87#define MSM_I2C_PHYS 0xA9900000
88#define MSM_I2C_SIZE SZ_4K
89
90#define MSM_HSUSB_PHYS 0xA0800000
91#define MSM_HSUSB_SIZE SZ_4K
92
93#define MSM_PMDH_PHYS 0xAA600000
94#define MSM_PMDH_SIZE SZ_4K
95
96#define MSM_EMDH_PHYS 0xAA700000
97#define MSM_EMDH_SIZE SZ_4K
98
99#define MSM_MDP_PHYS 0xAA200000
100#define MSM_MDP_SIZE 0x000F0000
101
102#define MSM_MDC_PHYS 0xAA500000
103#define MSM_MDC_SIZE SZ_1M
104
105#define MSM_AD5_PHYS 0xAC000000
106#define MSM_AD5_SIZE (SZ_1M*13)
107
108#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
deleted file mode 100644
index 198202c267c8..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H
24#define __ASM_ARCH_MSM_IOMAP_7X30_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_VIC_BASE IOMEM(0xE0000000)
39#define MSM_VIC_PHYS 0xC0080000
40#define MSM_VIC_SIZE SZ_4K
41
42#define MSM7X30_CSR_PHYS 0xC0100000
43#define MSM7X30_CSR_SIZE SZ_4K
44
45#define MSM_DMOV_BASE IOMEM(0xE0002000)
46#define MSM_DMOV_PHYS 0xAC400000
47#define MSM_DMOV_SIZE SZ_4K
48
49#define MSM7X30_GPIO1_PHYS 0xAC001000
50#define MSM7X30_GPIO1_SIZE SZ_4K
51
52#define MSM7X30_GPIO2_PHYS 0xAC101000
53#define MSM7X30_GPIO2_SIZE SZ_4K
54
55#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
56#define MSM_CLK_CTL_PHYS 0xAB800000
57#define MSM_CLK_CTL_SIZE SZ_4K
58
59#define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000)
60#define MSM_CLK_CTL_SH2_PHYS 0xABA01000
61#define MSM_CLK_CTL_SH2_SIZE SZ_4K
62
63#define MSM_ACC_BASE IOMEM(0xE0007000)
64#define MSM_ACC_PHYS 0xC0101000
65#define MSM_ACC_SIZE SZ_4K
66
67#define MSM_SAW_BASE IOMEM(0xE0008000)
68#define MSM_SAW_PHYS 0xC0102000
69#define MSM_SAW_SIZE SZ_4K
70
71#define MSM_GCC_BASE IOMEM(0xE0009000)
72#define MSM_GCC_PHYS 0xC0182000
73#define MSM_GCC_SIZE SZ_4K
74
75#define MSM_TCSR_BASE IOMEM(0xE000A000)
76#define MSM_TCSR_PHYS 0xAB600000
77#define MSM_TCSR_SIZE SZ_4K
78
79#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
80#define MSM_SHARED_RAM_PHYS 0x00100000
81#define MSM_SHARED_RAM_SIZE SZ_1M
82
83#define MSM_UART1_PHYS 0xACA00000
84#define MSM_UART1_SIZE SZ_4K
85
86#define MSM_UART2_PHYS 0xACB00000
87#define MSM_UART2_SIZE SZ_4K
88
89#define MSM_UART3_PHYS 0xACC00000
90#define MSM_UART3_SIZE SZ_4K
91
92#define MSM_MDC_BASE IOMEM(0xE0200000)
93#define MSM_MDC_PHYS 0xAA500000
94#define MSM_MDC_SIZE SZ_1M
95
96#define MSM_AD5_BASE IOMEM(0xE0300000)
97#define MSM_AD5_PHYS 0xA7000000
98#define MSM_AD5_SIZE (SZ_1M*13)
99
100#define MSM_HSUSB_PHYS 0xA3600000
101#define MSM_HSUSB_SIZE SZ_1K
102
103#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
deleted file mode 100644
index 0faa894729b7..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
24#define __ASM_ARCH_MSM_IOMAP_8X50_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_VIC_BASE IOMEM(0xE0000000)
39#define MSM_VIC_PHYS 0xAC000000
40#define MSM_VIC_SIZE SZ_4K
41
42#define QSD8X50_CSR_PHYS 0xAC100000
43#define QSD8X50_CSR_SIZE SZ_4K
44
45#define MSM_DMOV_BASE IOMEM(0xE0002000)
46#define MSM_DMOV_PHYS 0xA9700000
47#define MSM_DMOV_SIZE SZ_4K
48
49#define QSD8X50_GPIO1_PHYS 0xA9000000
50#define QSD8X50_GPIO1_SIZE SZ_4K
51
52#define QSD8X50_GPIO2_PHYS 0xA9100000
53#define QSD8X50_GPIO2_SIZE SZ_4K
54
55#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
56#define MSM_CLK_CTL_PHYS 0xA8600000
57#define MSM_CLK_CTL_SIZE SZ_4K
58
59#define MSM_SIRC_BASE IOMEM(0xE1006000)
60#define MSM_SIRC_PHYS 0xAC200000
61#define MSM_SIRC_SIZE SZ_4K
62
63#define MSM_SCPLL_BASE IOMEM(0xE1007000)
64#define MSM_SCPLL_PHYS 0xA8800000
65#define MSM_SCPLL_SIZE SZ_4K
66
67#ifdef CONFIG_MSM_SOC_REV_A
68#define MSM_SMI_BASE 0xE0000000
69#else
70#define MSM_SMI_BASE 0x00000000
71#endif
72
73#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
74#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
75#define MSM_SHARED_RAM_SIZE SZ_1M
76
77#define MSM_UART1_PHYS 0xA9A00000
78#define MSM_UART1_SIZE SZ_4K
79
80#define MSM_UART2_PHYS 0xA9B00000
81#define MSM_UART2_SIZE SZ_4K
82
83#define MSM_UART3_PHYS 0xA9C00000
84#define MSM_UART3_SIZE SZ_4K
85
86#define MSM_MDC_BASE IOMEM(0xE0200000)
87#define MSM_MDC_PHYS 0xAA500000
88#define MSM_MDC_SIZE SZ_1M
89
90#define MSM_AD5_BASE IOMEM(0xE0300000)
91#define MSM_AD5_PHYS 0xAC000000
92#define MSM_AD5_SIZE (SZ_1M*13)
93
94
95#define MSM_I2C_SIZE SZ_4K
96#define MSM_I2C_PHYS 0xA9900000
97
98#define MSM_HSUSB_PHYS 0xA0800000
99#define MSM_HSUSB_SIZE SZ_1K
100
101#define MSM_NAND_PHYS 0xA0A00000
102
103
104#define MSM_TSIF_PHYS (0xa0100000)
105#define MSM_TSIF_SIZE (0x200)
106
107#define MSM_TSSC_PHYS 0xAA300000
108
109#define MSM_UART1DM_PHYS 0xA0200000
110#define MSM_UART2DM_PHYS 0xA0900000
111
112
113#define MSM_SDC1_PHYS 0xA0300000
114#define MSM_SDC1_SIZE SZ_4K
115
116#define MSM_SDC2_PHYS 0xA0400000
117#define MSM_SDC2_SIZE SZ_4K
118
119#define MSM_SDC3_PHYS 0xA0500000
120#define MSM_SDC3_SIZE SZ_4K
121
122#define MSM_SDC4_PHYS 0xA0600000
123#define MSM_SDC4_SIZE SZ_4K
124
125#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
deleted file mode 100644
index 0e4f49157684..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_H
24#define __ASM_ARCH_MSM_IOMAP_H
25
26#include <asm/sizes.h>
27
28/* Physical base address and size of peripherals.
29 * Ordered by the virtual base addresses they will be mapped at.
30 *
31 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
32 * instruction, otherwise entry-macro.S will not compile.
33 *
34 * If you add or remove entries here, you'll want to edit the
35 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
36 * changes.
37 *
38 */
39
40#if defined(CONFIG_ARCH_MSM7X30)
41#include "msm_iomap-7x30.h"
42#elif defined(CONFIG_ARCH_QSD8X50)
43#include "msm_iomap-8x50.h"
44#else
45#include "msm_iomap-7x00.h"
46#endif
47
48/* Virtual addresses shared across all MSM targets. */
49#define MSM_CSR_BASE IOMEM(0xE0001000)
50#define MSM_GPIO1_BASE IOMEM(0xE0003000)
51#define MSM_GPIO2_BASE IOMEM(0xE0004000)
52
53#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
deleted file mode 100644
index 029463ec8756..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_smd.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/* linux/include/asm-arm/arch-msm/msm_smd.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_SMD_H
18#define __ASM_ARCH_MSM_SMD_H
19
20typedef struct smd_channel smd_channel_t;
21
22extern int (*msm_check_for_modem_crash)(void);
23
24/* warning: notify() may be called before open returns */
25int smd_open(const char *name, smd_channel_t **ch, void *priv,
26 void (*notify)(void *priv, unsigned event));
27
28#define SMD_EVENT_DATA 1
29#define SMD_EVENT_OPEN 2
30#define SMD_EVENT_CLOSE 3
31
32int smd_close(smd_channel_t *ch);
33
34/* passing a null pointer for data reads and discards */
35int smd_read(smd_channel_t *ch, void *data, int len);
36
37/* Write to stream channels may do a partial write and return
38** the length actually written.
39** Write to packet channels will never do a partial write --
40** it will return the requested length written or an error.
41*/
42int smd_write(smd_channel_t *ch, const void *data, int len);
43int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
44
45int smd_write_avail(smd_channel_t *ch);
46int smd_read_avail(smd_channel_t *ch);
47
48/* Returns the total size of the current packet being read.
49** Returns 0 if no packets available or a stream channel.
50*/
51int smd_cur_packet_size(smd_channel_t *ch);
52
53/* used for tty unthrottling and the like -- causes the notify()
54** callback to be called from the same lock context as is used
55** when it is called from channel updates
56*/
57void smd_kick(smd_channel_t *ch);
58
59
60#if 0
61/* these are interruptable waits which will block you until the specified
62** number of bytes are readable or writable.
63*/
64int smd_wait_until_readable(smd_channel_t *ch, int bytes);
65int smd_wait_until_writable(smd_channel_t *ch, int bytes);
66#endif
67
68typedef enum {
69 SMD_PORT_DS = 0,
70 SMD_PORT_DIAG,
71 SMD_PORT_RPC_CALL,
72 SMD_PORT_RPC_REPLY,
73 SMD_PORT_BT,
74 SMD_PORT_CONTROL,
75 SMD_PORT_MEMCPY_SPARE1,
76 SMD_PORT_DATA1,
77 SMD_PORT_DATA2,
78 SMD_PORT_DATA3,
79 SMD_PORT_DATA4,
80 SMD_PORT_DATA5,
81 SMD_PORT_DATA6,
82 SMD_PORT_DATA7,
83 SMD_PORT_DATA8,
84 SMD_PORT_DATA9,
85 SMD_PORT_DATA10,
86 SMD_PORT_DATA11,
87 SMD_PORT_DATA12,
88 SMD_PORT_DATA13,
89 SMD_PORT_DATA14,
90 SMD_PORT_DATA15,
91 SMD_PORT_DATA16,
92 SMD_PORT_DATA17,
93 SMD_PORT_DATA18,
94 SMD_PORT_DATA19,
95 SMD_PORT_DATA20,
96 SMD_PORT_GPS_NMEA,
97 SMD_PORT_BRIDGE_1,
98 SMD_PORT_BRIDGE_2,
99 SMD_PORT_BRIDGE_3,
100 SMD_PORT_BRIDGE_4,
101 SMD_PORT_BRIDGE_5,
102 SMD_PORT_LOOPBACK,
103 SMD_PORT_CS_APPS_MODEM,
104 SMD_PORT_CS_APPS_DSP,
105 SMD_PORT_CS_MODEM_DSP,
106 SMD_NUM_PORTS,
107} smd_port_id_type;
108
109#endif
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
deleted file mode 100644
index ef55868a5b8a..000000000000
--- a/arch/arm/mach-msm/include/mach/sirc.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_SIRC_H
14#define __ASM_ARCH_MSM_SIRC_H
15
16struct sirc_regs_t {
17 void *int_enable;
18 void *int_enable_clear;
19 void *int_enable_set;
20 void *int_type;
21 void *int_polarity;
22 void *int_clear;
23};
24
25struct sirc_cascade_regs {
26 void *int_status;
27 unsigned int cascade_irq;
28};
29
30void msm_init_sirc(void);
31void msm_sirc_enter_sleep(void);
32void msm_sirc_exit_sleep(void);
33
34#if defined(CONFIG_ARCH_MSM_SCORPION)
35
36#include <mach/msm_iomap.h>
37
38/*
39 * Secondary interrupt controller interrupts
40 */
41
42#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
43
44#define INT_UART1 (FIRST_SIRC_IRQ + 0)
45#define INT_UART2 (FIRST_SIRC_IRQ + 1)
46#define INT_UART3 (FIRST_SIRC_IRQ + 2)
47#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
48#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
49#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
50#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
51#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
52#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
53#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
54#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
55#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
56#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
57#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
58#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
59#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
60#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
61#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
62#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
63#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
64#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
65#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
66#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
67#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
68#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
69#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
70#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
71#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
72
73#if defined(CONFIG_MSM_SOC_REV_A)
74#define NR_SIRC_IRQS 28
75#define SIRC_MASK 0x0FFFFFFF
76#else
77#define NR_SIRC_IRQS 23
78#define SIRC_MASK 0x007FFFFF
79#endif
80
81#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
82
83#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
84#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
85#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
86#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
87#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
88#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
89#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
90#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
91#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
92#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
93#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
94#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
95
96#endif
97
98#endif
diff --git a/arch/arm/mach-msm/include/mach/vreg.h b/arch/arm/mach-msm/include/mach/vreg.h
deleted file mode 100644
index 6626e7864e28..000000000000
--- a/arch/arm/mach-msm/include/mach/vreg.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/include/asm-arm/arch-msm/vreg.h
2 *
3 * Copyright (C) 2008 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ARCH_ARM_MACH_MSM_VREG_H
18#define __ARCH_ARM_MACH_MSM_VREG_H
19
20struct vreg;
21
22struct vreg *vreg_get(struct device *dev, const char *id);
23void vreg_put(struct vreg *vreg);
24
25int vreg_enable(struct vreg *vreg);
26int vreg_disable(struct vreg *vreg);
27int vreg_set_level(struct vreg *vreg, unsigned mv);
28
29#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 10:03:02 -0500