aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-msm/include/mach
diff options
context:
space:
mode:
authorStepan Moskovchenko <stepanm@codeaurora.org>2010-08-24 22:51:15 -0400
committerDaniel Walker <dwalker@codeaurora.org>2010-10-08 18:12:52 -0400
commitd9c8279b326e18bcb25ee9d12fe7513d24f8bbb1 (patch)
treea2559867801db35cf1784e3e9cc91e25b80410e4 /arch/arm/mach-msm/include/mach
parentc6a5951ee53db0f275dd85a702325c981c8d8c4c (diff)
msm: Platform data for msm8x60 IOMMUs
Add the platform data for the IOMMUs found on the Qualcomm msm8x60 SoC. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include/mach')
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 88df7ca96f2d..45bab50e3ee6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -65,4 +65,37 @@
65#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) 65#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
66#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) 66#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
67 67
68#define MSM_IOMMU_JPEGD_PHYS 0x07300000
69#define MSM_IOMMU_JPEGD_SIZE SZ_1M
70
71#define MSM_IOMMU_VPE_PHYS 0x07400000
72#define MSM_IOMMU_VPE_SIZE SZ_1M
73
74#define MSM_IOMMU_MDP0_PHYS 0x07500000
75#define MSM_IOMMU_MDP0_SIZE SZ_1M
76
77#define MSM_IOMMU_MDP1_PHYS 0x07600000
78#define MSM_IOMMU_MDP1_SIZE SZ_1M
79
80#define MSM_IOMMU_ROT_PHYS 0x07700000
81#define MSM_IOMMU_ROT_SIZE SZ_1M
82
83#define MSM_IOMMU_IJPEG_PHYS 0x07800000
84#define MSM_IOMMU_IJPEG_SIZE SZ_1M
85
86#define MSM_IOMMU_VFE_PHYS 0x07900000
87#define MSM_IOMMU_VFE_SIZE SZ_1M
88
89#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
90#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
91
92#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
93#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
94
95#define MSM_IOMMU_GFX3D_PHYS 0x07C00000
96#define MSM_IOMMU_GFX3D_SIZE SZ_1M
97
98#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000
99#define MSM_IOMMU_GFX2D0_SIZE SZ_1M
100
68#endif 101#endif