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authorDavid Brown <davidb@codeaurora.org>2011-01-24 18:42:46 -0500
committerDavid Brown <davidb@codeaurora.org>2011-01-24 18:42:46 -0500
commit14847fdf3598109384e590a4154010f2ece6bb96 (patch)
tree613391138f0ec4c798befa7f7ea7f0479b71ec23 /arch/arm/mach-msm/devices-qsd8x50.c
parent75b0d32d5c0acd9b28f447aeddde5e94e5d64e5d (diff)
parent8b4d95fc76b85696c508f316810a6fbc15a7b8c5 (diff)
Merge branch 'msm-sdcc' into for-next
* msm-sdcc: msm: 8x50: Add initial support for SDCC mmc: msm_sdcc: Add gpio handling function to driver drivers: mmc: msm: remove clock disable in probe mmc: msm: fix dma usage not to use internal APIs
Diffstat (limited to 'arch/arm/mach-msm/devices-qsd8x50.c')
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c196
1 files changed, 196 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 93bddacad904..c9fa6552ff7d 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -125,6 +125,194 @@ struct platform_device msm_device_hsusb_host = {
125 }, 125 },
126}; 126};
127 127
128static struct resource resources_sdc1[] = {
129 {
130 .start = MSM_SDC1_PHYS,
131 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
132 .flags = IORESOURCE_MEM,
133 },
134 {
135 .start = INT_SDC1_0,
136 .end = INT_SDC1_0,
137 .flags = IORESOURCE_IRQ,
138 .name = "cmd_irq",
139 },
140 {
141 .start = INT_SDC1_1,
142 .end = INT_SDC1_1,
143 .flags = IORESOURCE_IRQ,
144 .name = "pio_irq",
145 },
146 {
147 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
148 .name = "status_irq"
149 },
150 {
151 .start = 8,
152 .end = 8,
153 .flags = IORESOURCE_DMA,
154 },
155};
156
157static struct resource resources_sdc2[] = {
158 {
159 .start = MSM_SDC2_PHYS,
160 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 {
164 .start = INT_SDC2_0,
165 .end = INT_SDC2_0,
166 .flags = IORESOURCE_IRQ,
167 .name = "cmd_irq",
168 },
169 {
170 .start = INT_SDC2_1,
171 .end = INT_SDC2_1,
172 .flags = IORESOURCE_IRQ,
173 .name = "pio_irq",
174 },
175 {
176 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
177 .name = "status_irq"
178 },
179 {
180 .start = 8,
181 .end = 8,
182 .flags = IORESOURCE_DMA,
183 },
184};
185
186static struct resource resources_sdc3[] = {
187 {
188 .start = MSM_SDC3_PHYS,
189 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
190 .flags = IORESOURCE_MEM,
191 },
192 {
193 .start = INT_SDC3_0,
194 .end = INT_SDC3_0,
195 .flags = IORESOURCE_IRQ,
196 .name = "cmd_irq",
197 },
198 {
199 .start = INT_SDC3_1,
200 .end = INT_SDC3_1,
201 .flags = IORESOURCE_IRQ,
202 .name = "pio_irq",
203 },
204 {
205 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
206 .name = "status_irq"
207 },
208 {
209 .start = 8,
210 .end = 8,
211 .flags = IORESOURCE_DMA,
212 },
213};
214
215static struct resource resources_sdc4[] = {
216 {
217 .start = MSM_SDC4_PHYS,
218 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .start = INT_SDC4_0,
223 .end = INT_SDC4_0,
224 .flags = IORESOURCE_IRQ,
225 .name = "cmd_irq",
226 },
227 {
228 .start = INT_SDC4_1,
229 .end = INT_SDC4_1,
230 .flags = IORESOURCE_IRQ,
231 .name = "pio_irq",
232 },
233 {
234 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
235 .name = "status_irq"
236 },
237 {
238 .start = 8,
239 .end = 8,
240 .flags = IORESOURCE_DMA,
241 },
242};
243
244struct platform_device msm_device_sdc1 = {
245 .name = "msm_sdcc",
246 .id = 1,
247 .num_resources = ARRAY_SIZE(resources_sdc1),
248 .resource = resources_sdc1,
249 .dev = {
250 .coherent_dma_mask = 0xffffffff,
251 },
252};
253
254struct platform_device msm_device_sdc2 = {
255 .name = "msm_sdcc",
256 .id = 2,
257 .num_resources = ARRAY_SIZE(resources_sdc2),
258 .resource = resources_sdc2,
259 .dev = {
260 .coherent_dma_mask = 0xffffffff,
261 },
262};
263
264struct platform_device msm_device_sdc3 = {
265 .name = "msm_sdcc",
266 .id = 3,
267 .num_resources = ARRAY_SIZE(resources_sdc3),
268 .resource = resources_sdc3,
269 .dev = {
270 .coherent_dma_mask = 0xffffffff,
271 },
272};
273
274struct platform_device msm_device_sdc4 = {
275 .name = "msm_sdcc",
276 .id = 4,
277 .num_resources = ARRAY_SIZE(resources_sdc4),
278 .resource = resources_sdc4,
279 .dev = {
280 .coherent_dma_mask = 0xffffffff,
281 },
282};
283
284static struct platform_device *msm_sdcc_devices[] __initdata = {
285 &msm_device_sdc1,
286 &msm_device_sdc2,
287 &msm_device_sdc3,
288 &msm_device_sdc4,
289};
290
291int __init msm_add_sdcc(unsigned int controller,
292 struct msm_mmc_platform_data *plat,
293 unsigned int stat_irq, unsigned long stat_irq_flags)
294{
295 struct platform_device *pdev;
296 struct resource *res;
297
298 if (controller < 1 || controller > 4)
299 return -EINVAL;
300
301 pdev = msm_sdcc_devices[controller-1];
302 pdev->dev.platform_data = plat;
303
304 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
305 if (!res)
306 return -EINVAL;
307 else if (stat_irq) {
308 res->start = res->end = stat_irq;
309 res->flags &= ~IORESOURCE_DISABLED;
310 res->flags |= stat_irq_flags;
311 }
312
313 return platform_device_register(pdev);
314}
315
128struct clk msm_clocks_8x50[] = { 316struct clk msm_clocks_8x50[] = {
129 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 317 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
130 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), 318 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
@@ -145,6 +333,14 @@ struct clk msm_clocks_8x50[] = {
145 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), 333 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
146 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), 334 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
147 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), 335 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
336 CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
337 CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF),
338 CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF),
339 CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF),
340 CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF),
341 CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF),
342 CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF),
343 CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF),
148 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), 344 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
149 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), 345 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
150 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), 346 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),