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authorDaniel Walker <dwalker@codeaurora.org>2010-03-30 19:11:56 -0400
committerDaniel Walker <dwalker@codeaurora.org>2010-06-17 15:55:41 -0400
commit8dadeea18be390bf3e5d47e6a8e2c752c7118b67 (patch)
tree860584aeb0533ca6964c9c31fa9706d987b551ec /arch/arm/mach-msm/board-trout-gpio.c
parent39b022ffcfbeb9e1d727db6404a1cf262c363e6e (diff)
arm: msm: trout: add trout specific gpio interrupts
This adds the interrupt layer onto the initial trout gpio changes. There changes were adapted from the Google driver which lists Arve Hjønnevåg <arve@android.com> as the author. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/board-trout-gpio.c')
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c115
1 files changed, 115 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 523d213bf79e..c50f3afc3134 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -15,10 +15,20 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/interrupt.h>
18#include <linux/gpio.h> 19#include <linux/gpio.h>
19 20
20#include "board-trout.h" 21#include "board-trout.h"
21 22
23static uint8_t trout_int_mask[2] = {
24 [0] = 0xff, /* mask all interrupts */
25 [1] = 0xff,
26};
27static uint8_t trout_sleep_int_mask[] = {
28 [0] = 0xff,
29 [1] = 0xff,
30};
31
22struct msm_gpio_chip { 32struct msm_gpio_chip {
23 struct gpio_chip chip; 33 struct gpio_chip chip;
24 void __iomem *reg; /* Base of register bank */ 34 void __iomem *reg; /* Base of register bank */
@@ -95,16 +105,121 @@ static struct msm_gpio_chip msm_gpio_banks[] = {
95 TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0), 105 TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
96}; 106};
97 107
108static void trout_gpio_irq_ack(unsigned int irq)
109{
110 int bank = TROUT_INT_TO_BANK(irq);
111 uint8_t mask = TROUT_INT_TO_MASK(irq);
112 int reg = TROUT_BANK_TO_STAT_REG(bank);
113 /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", irq);*/
114 writeb(mask, TROUT_CPLD_BASE + reg);
115}
116
117static void trout_gpio_irq_mask(unsigned int irq)
118{
119 unsigned long flags;
120 uint8_t reg_val;
121 int bank = TROUT_INT_TO_BANK(irq);
122 uint8_t mask = TROUT_INT_TO_MASK(irq);
123 int reg = TROUT_BANK_TO_MASK_REG(bank);
124
125 local_irq_save(flags);
126 reg_val = trout_int_mask[bank] |= mask;
127 /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
128 irq, bank, reg_val);*/
129 writeb(reg_val, TROUT_CPLD_BASE + reg);
130 local_irq_restore(flags);
131}
132
133static void trout_gpio_irq_unmask(unsigned int irq)
134{
135 unsigned long flags;
136 uint8_t reg_val;
137 int bank = TROUT_INT_TO_BANK(irq);
138 uint8_t mask = TROUT_INT_TO_MASK(irq);
139 int reg = TROUT_BANK_TO_MASK_REG(bank);
140
141 local_irq_save(flags);
142 reg_val = trout_int_mask[bank] &= ~mask;
143 /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
144 irq, bank, reg_val);*/
145 writeb(reg_val, TROUT_CPLD_BASE + reg);
146 local_irq_restore(flags);
147}
148
149int trout_gpio_irq_set_wake(unsigned int irq, unsigned int on)
150{
151 unsigned long flags;
152 int bank = TROUT_INT_TO_BANK(irq);
153 uint8_t mask = TROUT_INT_TO_MASK(irq);
154
155 local_irq_save(flags);
156 if(on)
157 trout_sleep_int_mask[bank] &= ~mask;
158 else
159 trout_sleep_int_mask[bank] |= mask;
160 local_irq_restore(flags);
161 return 0;
162}
163
164static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
165{
166 int j, m;
167 unsigned v;
168 int bank;
169 int stat_reg;
170 int int_base = TROUT_INT_START;
171 uint8_t int_mask;
172
173 for (bank = 0; bank < 2; bank++) {
174 stat_reg = TROUT_BANK_TO_STAT_REG(bank);
175 v = readb(TROUT_CPLD_BASE + stat_reg);
176 int_mask = trout_int_mask[bank];
177 if (v & int_mask) {
178 writeb(v & int_mask, TROUT_CPLD_BASE + stat_reg);
179 printk(KERN_ERR "trout_gpio_irq_handler: got masked "
180 "interrupt: %d:%02x\n", bank, v & int_mask);
181 }
182 v &= ~int_mask;
183 while (v) {
184 m = v & -v;
185 j = fls(m) - 1;
186 /*printk(KERN_INFO "msm_gpio_irq_handler %d:%02x %02x b"
187 "it %d irq %d\n", bank, v, m, j, int_base + j);*/
188 v &= ~m;
189 generic_handle_irq(int_base + j);
190 }
191 int_base += TROUT_INT_BANK0_COUNT;
192 }
193 desc->chip->ack(irq);
194}
195
196static struct irq_chip trout_gpio_irq_chip = {
197 .name = "troutgpio",
198 .ack = trout_gpio_irq_ack,
199 .mask = trout_gpio_irq_mask,
200 .unmask = trout_gpio_irq_unmask,
201 .set_wake = trout_gpio_irq_set_wake,
202};
203
98/* 204/*
99 * Called from the processor-specific init to enable GPIO pin support. 205 * Called from the processor-specific init to enable GPIO pin support.
100 */ 206 */
101int __init trout_init_gpio(void) 207int __init trout_init_gpio(void)
102{ 208{
103 int i; 209 int i;
210 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
211 set_irq_chip(i, &trout_gpio_irq_chip);
212 set_irq_handler(i, handle_edge_irq);
213 set_irq_flags(i, IRQF_VALID);
214 }
104 215
105 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) 216 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
106 gpiochip_add(&msm_gpio_banks[i].chip); 217 gpiochip_add(&msm_gpio_banks[i].chip);
107 218
219 set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
220 set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
221 set_irq_wake(MSM_GPIO_TO_INT(17), 1);
222
108 return 0; 223 return 0;
109} 224}
110 225