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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-12-04 10:55:14 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-14 14:21:30 -0500
commitb580b899dd05a007ad232ee49a07b32d91876462 (patch)
tree72def6f195ca02a5f9eb5e082930603b85349b0e /arch/arm/mach-msm/board-msm8x60.c
parente745a6676c76280f9721adeec79b08a0f2dfcc21 (diff)
ARM: GIC: provide a single initialization function for boot CPU
Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-msm/board-msm8x60.c')
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 7486a681cc71..aaf8ec8a1495 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -44,9 +44,8 @@ static void __init msm8x60_init_irq(void)
44{ 44{
45 unsigned int i; 45 unsigned int i;
46 46
47 gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
48 gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; 47 gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
49 gic_cpu_init(0, MSM_QGIC_CPU_BASE); 48 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, gic_cpu_base_addr);
50 49
51 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ 50 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
52 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); 51 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);