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authorHaojian Zhuang <haojian.zhuang@marvell.com>2009-12-04 09:41:28 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-03-01 18:40:55 -0500
commit2f7e8faef5a50efaa1c173e99bdaa29e0129bb99 (patch)
treec73ae01004e110a87b7cf6cae686b9c142e2a63b /arch/arm/mach-mmp
parent978da5bcdb33f6e030fa3304662e2455a018f1b0 (diff)
[ARM] mmp: add support for Marvell MMP2
Marvell MMP2 (aka ARMADA610) is a SoC based on PJ4 core. It's ARMv6 compatible. Support basic interrupt handler and timer, and basic support for MMP2 based FLINT platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r--arch/arm/mach-mmp/Kconfig18
-rw-r--r--arch/arm/mach-mmp/Makefile2
-rw-r--r--arch/arm/mach-mmp/common.h2
-rw-r--r--arch/arm/mach-mmp/flint.c123
-rw-r--r--arch/arm/mach-mmp/include/mach/cputype.h9
-rw-r--r--arch/arm/mach-mmp/include/mach/devices.h12
-rw-r--r--arch/arm/mach-mmp/include/mach/entry-macro.S7
-rw-r--r--arch/arm/mach-mmp/include/mach/irqs.h109
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-mmp2.h236
-rw-r--r--arch/arm/mach-mmp/include/mach/mmp2.h60
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apbc.h41
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-icu.h30
-rw-r--r--arch/arm/mach-mmp/irq-mmp2.c138
-rw-r--r--arch/arm/mach-mmp/mmp2.c83
-rw-r--r--arch/arm/mach-mmp/time.c26
15 files changed, 890 insertions, 6 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index daddbefebf44..91631201e3f5 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -1,6 +1,6 @@
1if ARCH_MMP 1if ARCH_MMP
2 2
3menu "Marvell PXA168/910 Implmentations" 3menu "Marvell PXA168/910/MMP2 Implmentations"
4 4
5config MACH_ASPENITE 5config MACH_ASPENITE
6 bool "Marvell's PXA168 Aspenite Development Board" 6 bool "Marvell's PXA168 Aspenite Development Board"
@@ -37,6 +37,16 @@ config MACH_TTC_DKB
37 Say 'Y' here if you want to support the Marvell PXA910-based 37 Say 'Y' here if you want to support the Marvell PXA910-based
38 TTC_DKB Development Board. 38 TTC_DKB Development Board.
39 39
40config MACH_FLINT
41 bool "Marvell's Flint Development Platform"
42 select CPU_MMP2
43 help
44 Say 'Y' here if you want to support the Marvell MMP2-based
45 Flint Development Platform.
46 MMP2-based board can't be co-existed with PXA168-based &
47 PXA910-based development board. Since MMP2 is compatible to
48 ARMv6 architecture.
49
40endmenu 50endmenu
41 51
42config CPU_PXA168 52config CPU_PXA168
@@ -51,4 +61,10 @@ config CPU_PXA910
51 help 61 help
52 Select code specific to PXA910 62 Select code specific to PXA910
53 63
64config CPU_MMP2
65 bool
66 select CPU_V6
67 select CPU_32v6K
68 help
69 Select code specific to MMP2. MMP2 is ARMv6 compatible.
54endif 70endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index d4debb39023c..698cd996cde9 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -7,6 +7,7 @@ obj-y += common.o clock.o devices.o time.o
7# SoC support 7# SoC support
8obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o 8obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o
9obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o 9obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o
10obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o
10 11
11# board support 12# board support
12obj-$(CONFIG_MACH_ASPENITE) += aspenite.o 13obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
@@ -14,3 +15,4 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
14obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o 15obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
15obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o 16obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
16obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o 17obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
18obj-$(CONFIG_MACH_FLINT) += flint.o
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index c33fbbc49417..85bf12451433 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -6,8 +6,10 @@ extern void timer_init(int irq);
6 6
7extern struct sys_timer pxa168_timer; 7extern struct sys_timer pxa168_timer;
8extern struct sys_timer pxa910_timer; 8extern struct sys_timer pxa910_timer;
9extern struct sys_timer mmp2_timer;
9extern void __init pxa168_init_irq(void); 10extern void __init pxa168_init_irq(void);
10extern void __init pxa910_init_irq(void); 11extern void __init pxa910_init_irq(void);
12extern void __init mmp2_init_irq(void);
11 13
12extern void __init icu_init_irq(void); 14extern void __init icu_init_irq(void);
13extern void __init pxa_map_io(void); 15extern void __init pxa_map_io(void);
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
new file mode 100644
index 000000000000..4ec7709a3462
--- /dev/null
+++ b/arch/arm/mach-mmp/flint.c
@@ -0,0 +1,123 @@
1/*
2 * linux/arch/arm/mach-mmp/flint.c
3 *
4 * Support for the Marvell Flint Development Platform.
5 *
6 * Copyright (C) 2009 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * publishhed by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/smc91x.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <mach/addr-map.h>
23#include <mach/mfp-mmp2.h>
24#include <mach/mmp2.h>
25
26#include "common.h"
27
28static unsigned long flint_pin_config[] __initdata = {
29 /* UART1 */
30 GPIO45_UART1_RXD,
31 GPIO46_UART1_TXD,
32
33 /* UART2 */
34 GPIO47_UART2_RXD,
35 GPIO48_UART2_TXD,
36
37 /* SMC */
38 GPIO151_SMC_SCLK,
39 GPIO145_SMC_nCS0,
40 GPIO146_SMC_nCS1,
41 GPIO152_SMC_BE0,
42 GPIO153_SMC_BE1,
43 GPIO154_SMC_IRQ,
44 GPIO113_SMC_RDY,
45
46 /*Ethernet*/
47 GPIO155_GPIO155,
48
49 /* DFI */
50 GPIO168_DFI_D0,
51 GPIO167_DFI_D1,
52 GPIO166_DFI_D2,
53 GPIO165_DFI_D3,
54 GPIO107_DFI_D4,
55 GPIO106_DFI_D5,
56 GPIO105_DFI_D6,
57 GPIO104_DFI_D7,
58 GPIO111_DFI_D8,
59 GPIO164_DFI_D9,
60 GPIO163_DFI_D10,
61 GPIO162_DFI_D11,
62 GPIO161_DFI_D12,
63 GPIO110_DFI_D13,
64 GPIO109_DFI_D14,
65 GPIO108_DFI_D15,
66 GPIO143_ND_nCS0,
67 GPIO144_ND_nCS1,
68 GPIO147_ND_nWE,
69 GPIO148_ND_nRE,
70 GPIO150_ND_ALE,
71 GPIO149_ND_CLE,
72 GPIO112_ND_RDY0,
73 GPIO160_ND_RDY1,
74};
75
76static struct smc91x_platdata flint_smc91x_info = {
77 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
78};
79
80static struct resource smc91x_resources[] = {
81 [0] = {
82 .start = SMC_CS1_PHYS_BASE + 0x300,
83 .end = SMC_CS1_PHYS_BASE + 0xfffff,
84 .flags = IORESOURCE_MEM,
85 },
86 [1] = {
87 .start = gpio_to_irq(155),
88 .end = gpio_to_irq(155),
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
90 }
91};
92
93static struct platform_device smc91x_device = {
94 .name = "smc91x",
95 .id = 0,
96 .dev = {
97 .platform_data = &flint_smc91x_info,
98 },
99 .num_resources = ARRAY_SIZE(smc91x_resources),
100 .resource = smc91x_resources,
101};
102
103static void __init flint_init(void)
104{
105 mfp_config(ARRAY_AND_SIZE(flint_pin_config));
106
107 /* on-chip devices */
108 mmp2_add_uart(1);
109 mmp2_add_uart(2);
110
111 /* off-chip devices */
112 platform_device_register(&smc91x_device);
113}
114
115MACHINE_START(FLINT, "Flint Development Platform")
116 .phys_io = APB_PHYS_BASE,
117 .boot_params = 0x00000100,
118 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
119 .map_io = pxa_map_io,
120 .init_irq = mmp2_init_irq,
121 .timer = &mmp2_timer,
122 .init_machine = flint_init,
123MACHINE_END
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index 25e797b09083..83b18721d933 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * PXA168 A0 0x41159263 0x56158400 0x00A0A333 9 * PXA168 A0 0x41159263 0x56158400 0x00A0A333
10 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 10 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910
11 * MMP2 Z0 0x560f5811
11 */ 12 */
12 13
13#ifdef CONFIG_CPU_PXA168 14#ifdef CONFIG_CPU_PXA168
@@ -24,7 +25,15 @@
24# define __cpu_is_pxa910(id) (0) 25# define __cpu_is_pxa910(id) (0)
25#endif 26#endif
26 27
28#ifdef CONFIG_CPU_MMP2
29# define __cpu_is_mmp2(id) \
30 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; })
31#else
32# define __cpu_is_mmp2(id) (0)
33#endif
34
27#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) 35#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
28#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) 36#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
37#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); })
29 38
30#endif /* __ASM_MACH_CPUTYPE_H */ 39#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
index 24585397217e..1fa0a492454a 100644
--- a/arch/arm/mach-mmp/include/mach/devices.h
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -34,4 +34,16 @@ struct pxa_device_desc pxa910_device_##_name __initdata = { \
34 .size = _size, \ 34 .size = _size, \
35 .dma = { _dma }, \ 35 .dma = { _dma }, \
36}; 36};
37
38#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
39struct pxa_device_desc mmp2_device_##_name __initdata = { \
40 .dev_name = "mmp2-" #_name, \
41 .drv_name = _drv, \
42 .id = _id, \
43 .irq = IRQ_MMP2_##_irq, \
44 .start = _start, \
45 .size = _size, \
46 .dma = { _dma }, \
47}
48
37extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); 49extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 6d3cd35478b5..c42d9d4e892d 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -15,7 +15,12 @@
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =ICU_AP_IRQ_SEL_INT_NUM 18 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
19 and \tmp, \tmp, #0xff00
20 cmp \tmp, #0x5800
21 ldr \base, =ICU_VIRT_BASE
22 addne \base, \base, #0x10c @ PJ1 AP INT SEL register
23 addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
19 .endm 24 .endm
20 25
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index d68871b0f28c..f907cc9e08e1 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -113,8 +113,113 @@
113#define IRQ_PXA910_AP_PMU 60 113#define IRQ_PXA910_AP_PMU 60
114#define IRQ_PXA910_SM_INT 63 /* from PinMux */ 114#define IRQ_PXA910_SM_INT 63 /* from PinMux */
115 115
116#define IRQ_GPIO_START 64 116/*
117#define IRQ_GPIO_NUM 128 117 * Interrupt numbers for MMP2
118 */
119#define IRQ_MMP2_NONE (-1)
120#define IRQ_MMP2_SSP1 0
121#define IRQ_MMP2_SSP2 1
122#define IRQ_MMP2_SSPA1 2
123#define IRQ_MMP2_SSPA2 3
124#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */
125#define IRQ_MMP2_RTC_MUX 5
126#define IRQ_MMP2_TWSI1 7
127#define IRQ_MMP2_GPU 8
128#define IRQ_MMP2_KEYPAD 9
129#define IRQ_MMP2_ROTARY 10
130#define IRQ_MMP2_TRACKBALL 11
131#define IRQ_MMP2_ONEWIRE 12
132#define IRQ_MMP2_TIMER1 13
133#define IRQ_MMP2_TIMER2 14
134#define IRQ_MMP2_TIMER3 15
135#define IRQ_MMP2_RIPC 16
136#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */
137#define IRQ_MMP2_HDMI 19
138#define IRQ_MMP2_SSP3 20
139#define IRQ_MMP2_SSP4 21
140#define IRQ_MMP2_USB_HS1 22
141#define IRQ_MMP2_USB_HS2 23
142#define IRQ_MMP2_UART3 24
143#define IRQ_MMP2_UART1 27
144#define IRQ_MMP2_UART2 28
145#define IRQ_MMP2_MIPI_DSI 29
146#define IRQ_MMP2_CI2 30
147#define IRQ_MMP2_PMU_TIMER1 31
148#define IRQ_MMP2_PMU_TIMER2 32
149#define IRQ_MMP2_PMU_TIMER3 33
150#define IRQ_MMP2_USB_FS 34
151#define IRQ_MMP2_MISC_MUX 35
152#define IRQ_MMP2_WDT1 36
153#define IRQ_MMP2_NAND_DMA 37
154#define IRQ_MMP2_USIM 38
155#define IRQ_MMP2_MMC 39
156#define IRQ_MMP2_WTM 40
157#define IRQ_MMP2_LCD 41
158#define IRQ_MMP2_CI 42
159#define IRQ_MMP2_IRE 43
160#define IRQ_MMP2_USB_OTG 44
161#define IRQ_MMP2_NAND 45
162#define IRQ_MMP2_UART4 46
163#define IRQ_MMP2_DMA_FIQ 47
164#define IRQ_MMP2_DMA_RIQ 48
165#define IRQ_MMP2_GPIO 49
166#define IRQ_MMP2_SSP_MUX 51
167#define IRQ_MMP2_MMC2 52
168#define IRQ_MMP2_MMC3 53
169#define IRQ_MMP2_MMC4 54
170#define IRQ_MMP2_MIPI_HSI 55
171#define IRQ_MMP2_MSP 58
172#define IRQ_MMP2_MIPI_SLIM_DMA 59
173#define IRQ_MMP2_PJ4_FREQ_CHG 60
174#define IRQ_MMP2_MIPI_SLIM 62
175#define IRQ_MMP2_SM 63
176
177#define IRQ_MMP2_MUX_BASE 64
178
179/* secondary interrupt of INT #4 */
180#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE)
181#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0)
182#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1)
183
184/* secondary interrupt of INT #5 */
185#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2)
186#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0)
187#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1)
188
189/* secondary interrupt of INT #17 */
190#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2)
191#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0)
192#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1)
193#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2)
194#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3)
195#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4)
196
197/* secondary interrupt of INT #35 */
198#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5)
199#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0)
200#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1)
201#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2)
202#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3)
203#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4)
204#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5)
205#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6)
206#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7)
207#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9)
208#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10)
209#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11)
210#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12)
211#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13)
212#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14)
213
214/* secondary interrupt of INT #51 */
215#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15)
216#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0)
217#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1)
218
219#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2)
220
221#define IRQ_GPIO_START 128
222#define IRQ_GPIO_NUM 192
118#define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) 223#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
119 224
120#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) 225#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
new file mode 100644
index 000000000000..937151085349
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -0,0 +1,236 @@
1#ifndef __ASM_MACH_MFP_MMP2_H
2#define __ASM_MACH_MFP_MMP2_H
3
4#include <mach/mfp.h>
5
6#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
7#define MFP_DRIVE_SLOW (0x2 << 13)
8#define MFP_DRIVE_MEDIUM (0x4 << 13)
9#define MFP_DRIVE_FAST (0x8 << 13)
10
11/* GPIO */
12
13/* DFI */
14#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)
15#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0)
16#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0)
17#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0)
18#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0)
19#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0)
20#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0)
21#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0)
22#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0)
23#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0)
24#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0)
25#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0)
26#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0)
27#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0)
28#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0)
29#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0)
30#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0)
31#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0)
32#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0)
33#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0)
34#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0)
35#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0)
36#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0)
37#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0)
38
39/* Static Memory Controller */
40#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0)
41#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0)
42#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0)
43#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0)
44#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0)
45#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0)
46#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0)
47
48/* Ethernet */
49#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2)
50#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1)
51
52/* UART1 */
53#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1)
54#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1)
55#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1)
56#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1)
57#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1)
58#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1)
59
60/* UART2 */
61#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1)
62#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1)
63#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1)
64#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1)
65
66/* UART3 */
67#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1)
68#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1)
69#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1)
70#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1)
71
72/* MMC1 */
73#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST)
74#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST)
75#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST)
76#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST)
77#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST)
78#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST)
79#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST)
80#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST)
81#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST)
82#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST)
83#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST)
84#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST)
85
86/*MMC2*/
87#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST)
88#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST)
89#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST)
90#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST)
91#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST)
92#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST)
93
94/*MMC3*/
95#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST)
96#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST)
97#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST)
98#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST)
99#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST)
100#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST)
101#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST)
102#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST)
103#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST)
104#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST)
105
106/* LCD */
107#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST)
108#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST)
109#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST)
110#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST)
111#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST)
112#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST)
113#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST)
114#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST)
115#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST)
116#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST)
117#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST)
118#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST)
119#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST)
120#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST)
121#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST)
122#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST)
123#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST)
124#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST)
125#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST)
126#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST)
127#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST)
128#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST)
129#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST)
130#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST)
131#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST)
132#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST)
133#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST)
134#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST)
135#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST)
136#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST)
137#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST)
138#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST)
139#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST)
140
141#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST)
142
143/*LCD TV path*/
144#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST)
145#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST)
146#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST)
147#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST)
148#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST)
149#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST)
150#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST)
151#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST)
152#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST)
153#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST)
154#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST)
155#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST)
156
157/* I2C */
158#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW)
159#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW)
160#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW)
161#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW)
162#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW)
163#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW)
164#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW)
165#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW)
166
167/* SSPA1 */
168#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1)
169#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1)
170#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1)
171#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1)
172#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1)
173#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1)
174
175/* SSPA2 */
176#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1)
177#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1)
178#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1)
179#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1)
180
181/* Keypad */
182#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
183#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
184#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
185#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
186#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
187#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
188#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
189#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
190#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
191#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
192#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
193#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
194#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
195#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
196#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
197#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
198#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
199#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
200#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
201#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
202#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1)
203#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1)
204#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1)
205#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1)
206
207/* CAMERA */
208#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST)
209#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST)
210#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST)
211#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST)
212#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST)
213#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST)
214#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST)
215#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST)
216#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST)
217#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST)
218#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST)
219#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST)
220
221/* Wifi */
222#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0)
223#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0)
224#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0)
225#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0)
226#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0)
227#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0)
228#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0)
229#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0)
230
231/* Codec*/
232#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0)
233
234
235#endif /* __ASM_MACH_MFP_MMP2_H */
236
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
new file mode 100644
index 000000000000..459f3be9cfb2
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -0,0 +1,60 @@
1#ifndef __ASM_MACH_MMP2_H
2#define __ASM_MACH_MMP2_H
3
4#include <linux/i2c.h>
5#include <mach/devices.h>
6#include <plat/i2c.h>
7
8extern struct pxa_device_desc mmp2_device_uart1;
9extern struct pxa_device_desc mmp2_device_uart2;
10extern struct pxa_device_desc mmp2_device_uart3;
11extern struct pxa_device_desc mmp2_device_uart4;
12extern struct pxa_device_desc mmp2_device_twsi1;
13extern struct pxa_device_desc mmp2_device_twsi2;
14extern struct pxa_device_desc mmp2_device_twsi3;
15extern struct pxa_device_desc mmp2_device_twsi4;
16extern struct pxa_device_desc mmp2_device_twsi5;
17extern struct pxa_device_desc mmp2_device_twsi6;
18
19static inline int mmp2_add_uart(int id)
20{
21 struct pxa_device_desc *d = NULL;
22
23 switch (id) {
24 case 1: d = &mmp2_device_uart1; break;
25 case 2: d = &mmp2_device_uart2; break;
26 case 3: d = &mmp2_device_uart3; break;
27 case 4: d = &mmp2_device_uart4; break;
28 default:
29 return -EINVAL;
30 }
31
32 return pxa_register_device(d, NULL, 0);
33}
34
35static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
36 struct i2c_board_info *info, unsigned size)
37{
38 struct pxa_device_desc *d = NULL;
39 int ret;
40
41 switch (id) {
42 case 0: d = &mmp2_device_twsi1; break;
43 case 1: d = &mmp2_device_twsi2; break;
44 case 2: d = &mmp2_device_twsi3; break;
45 case 3: d = &mmp2_device_twsi4; break;
46 case 4: d = &mmp2_device_twsi5; break;
47 case 5: d = &mmp2_device_twsi6; break;
48 default:
49 return -EINVAL;
50 }
51
52 ret = i2c_register_board_info(id, info, size);
53 if (ret)
54 return ret;
55
56 return pxa_register_device(d, data, sizeof(*data));
57}
58
59#endif /* __ASM_MACH_MMP2_H */
60
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 98ccbee4bd0c..712af03fd1af 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -69,6 +69,47 @@
69#define APBC_PXA910_ASFAR APBC_REG(0x050) 69#define APBC_PXA910_ASFAR APBC_REG(0x050)
70#define APBC_PXA910_ASSAR APBC_REG(0x054) 70#define APBC_PXA910_ASSAR APBC_REG(0x054)
71 71
72/*
73 * APB Clock register offsets for MMP2
74 */
75#define APBC_MMP2_RTC APBC_REG(0x000)
76#define APBC_MMP2_TWSI1 APBC_REG(0x004)
77#define APBC_MMP2_TWSI2 APBC_REG(0x008)
78#define APBC_MMP2_TWSI3 APBC_REG(0x00c)
79#define APBC_MMP2_TWSI4 APBC_REG(0x010)
80#define APBC_MMP2_ONEWIRE APBC_REG(0x014)
81#define APBC_MMP2_KPC APBC_REG(0x018)
82#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c)
83#define APBC_MMP2_SW_JTAG APBC_REG(0x020)
84#define APBC_MMP2_TIMERS APBC_REG(0x024)
85#define APBC_MMP2_UART1 APBC_REG(0x02c)
86#define APBC_MMP2_UART2 APBC_REG(0x030)
87#define APBC_MMP2_UART3 APBC_REG(0x034)
88#define APBC_MMP2_GPIO APBC_REG(0x038)
89#define APBC_MMP2_PWM0 APBC_REG(0x03c)
90#define APBC_MMP2_PWM1 APBC_REG(0x040)
91#define APBC_MMP2_PWM2 APBC_REG(0x044)
92#define APBC_MMP2_PWM3 APBC_REG(0x048)
93#define APBC_MMP2_SSP0 APBC_REG(0x04c)
94#define APBC_MMP2_SSP1 APBC_REG(0x050)
95#define APBC_MMP2_SSP2 APBC_REG(0x054)
96#define APBC_MMP2_SSP3 APBC_REG(0x058)
97#define APBC_MMP2_SSP4 APBC_REG(0x05c)
98#define APBC_MMP2_SSP5 APBC_REG(0x060)
99#define APBC_MMP2_AIB APBC_REG(0x064)
100#define APBC_MMP2_ASFAR APBC_REG(0x068)
101#define APBC_MMP2_ASSAR APBC_REG(0x06c)
102#define APBC_MMP2_USIM APBC_REG(0x070)
103#define APBC_MMP2_MPMU APBC_REG(0x074)
104#define APBC_MMP2_IPC APBC_REG(0x078)
105#define APBC_MMP2_TWSI5 APBC_REG(0x07c)
106#define APBC_MMP2_TWSI6 APBC_REG(0x080)
107#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084)
108#define APBC_MMP2_UART4 APBC_REG(0x088)
109#define APBC_MMP2_RIPC APBC_REG(0x08c)
110#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */
111#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
112
72/* Common APB clock register bit definitions */ 113/* Common APB clock register bit definitions */
73#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ 114#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
74#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ 115#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h
index e5f08723e0cc..02b8bf83acb3 100644
--- a/arch/arm/mach-mmp/include/mach/regs-icu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-icu.h
@@ -17,10 +17,12 @@
17#define ICU_REG(x) (ICU_VIRT_BASE + (x)) 17#define ICU_REG(x) (ICU_VIRT_BASE + (x))
18 18
19#define ICU_INT_CONF(n) ICU_REG((n) << 2) 19#define ICU_INT_CONF(n) ICU_REG((n) << 2)
20#define ICU_INT_CONF_MASK (0xf)
21
22/************ PXA168/PXA910 (MMP) *********************/
20#define ICU_INT_CONF_AP_INT (1 << 6) 23#define ICU_INT_CONF_AP_INT (1 << 6)
21#define ICU_INT_CONF_CP_INT (1 << 5) 24#define ICU_INT_CONF_CP_INT (1 << 5)
22#define ICU_INT_CONF_IRQ (1 << 4) 25#define ICU_INT_CONF_IRQ (1 << 4)
23#define ICU_INT_CONF_MASK (0xf)
24 26
25#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ 27#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ 28#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
@@ -28,4 +30,30 @@
28#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ 30#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ 31#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
30 32
33/************************** MMP2 ***********************/
34
35/*
36 * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
37 * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
38 */
39#define ICU_INT_ROUTE_SP_IRQ (1 << 4)
40#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
41#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
42
43#define MMP2_ICU_INT4_STATUS ICU_REG(0x150)
44#define MMP2_ICU_INT5_STATUS ICU_REG(0x154)
45#define MMP2_ICU_INT17_STATUS ICU_REG(0x158)
46#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c)
47#define MMP2_ICU_INT51_STATUS ICU_REG(0x160)
48
49#define MMP2_ICU_INT4_MASK ICU_REG(0x168)
50#define MMP2_ICU_INT5_MASK ICU_REG(0x16C)
51#define MMP2_ICU_INT17_MASK ICU_REG(0x170)
52#define MMP2_ICU_INT35_MASK ICU_REG(0x174)
53#define MMP2_ICU_INT51_MASK ICU_REG(0x178)
54
55#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100)
56#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104)
57#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108)
58
31#endif /* __ASM_MACH_ICU_H */ 59#endif /* __ASM_MACH_ICU_H */
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
new file mode 100644
index 000000000000..dcd36f4bc9de
--- /dev/null
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -0,0 +1,138 @@
1/*
2 * linux/arch/arm/mach-mmp/irq-mmp2.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
7 * Copyright: Marvell International Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17
18#include <mach/regs-icu.h>
19
20#include "common.h"
21
22static void icu_mask_irq(unsigned int irq)
23{
24 uint32_t r = __raw_readl(ICU_INT_CONF(irq));
25
26 r &= ~ICU_INT_ROUTE_PJ4_IRQ;
27 __raw_writel(r, ICU_INT_CONF(irq));
28}
29
30static void icu_unmask_irq(unsigned int irq)
31{
32 uint32_t r = __raw_readl(ICU_INT_CONF(irq));
33
34 r |= ICU_INT_ROUTE_PJ4_IRQ;
35 __raw_writel(r, ICU_INT_CONF(irq));
36}
37
38static struct irq_chip icu_irq_chip = {
39 .name = "icu_irq",
40 .mask_ack = icu_mask_irq,
41 .unmask = icu_unmask_irq,
42};
43
44#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
45static void _name_##_mask_irq(unsigned int irq) \
46{ \
47 uint32_t r; \
48 r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \
49 __raw_writel(r, prefix##_MASK); \
50}
51
52#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
53static void _name_##_unmask_irq(unsigned int irq) \
54{ \
55 uint32_t r; \
56 r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \
57 __raw_writel(r, prefix##_MASK); \
58}
59
60#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
61static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
62{ \
63 unsigned long status, mask, n; \
64 mask = __raw_readl(prefix##_MASK); \
65 while (1) { \
66 status = __raw_readl(prefix##_STATUS) & ~mask; \
67 if (status == 0) \
68 break; \
69 n = find_first_bit(&status, BITS_PER_LONG); \
70 while (n < BITS_PER_LONG) { \
71 generic_handle_irq(irq_base + n); \
72 n = find_next_bit(&status, BITS_PER_LONG, n+1); \
73 } \
74 } \
75}
76
77#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \
78SECOND_IRQ_MASK(_name_, irq_base, prefix) \
79SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
80SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
81static struct irq_chip _name_##_irq_chip = { \
82 .name = #_name_, \
83 .mask_ack = _name_##_mask_irq, \
84 .unmask = _name_##_unmask_irq, \
85}
86
87SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
88SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5);
89SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
90SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
91SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51);
92
93static void init_mux_irq(struct irq_chip *chip, int start, int num)
94{
95 int irq;
96
97 for (irq = start; num > 0; irq++, num--) {
98 chip->mask_ack(irq);
99 set_irq_chip(irq, chip);
100 set_irq_flags(irq, IRQF_VALID);
101 set_irq_handler(irq, handle_level_irq);
102 }
103}
104
105void __init mmp2_init_irq(void)
106{
107 int irq;
108
109 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
110 icu_mask_irq(irq);
111 set_irq_chip(irq, &icu_irq_chip);
112 set_irq_flags(irq, IRQF_VALID);
113
114 switch (irq) {
115 case IRQ_MMP2_PMIC_MUX:
116 case IRQ_MMP2_RTC_MUX:
117 case IRQ_MMP2_TWSI_MUX:
118 case IRQ_MMP2_MISC_MUX:
119 case IRQ_MMP2_SSP_MUX:
120 break;
121 default:
122 set_irq_handler(irq, handle_level_irq);
123 break;
124 }
125 }
126
127 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
128 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
129 init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
130 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
131 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
132
133 set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
134 set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
135 set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
136 set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
137 set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
138}
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
new file mode 100644
index 000000000000..a9ca93d97412
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -0,0 +1,83 @@
1/*
2 * linux/arch/arm/mach-mmp/mmp2.c
3 *
4 * code name MMP2
5 *
6 * Copyright (C) 2009 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17
18#include <mach/addr-map.h>
19#include <mach/regs-apbc.h>
20#include <mach/regs-apmu.h>
21#include <mach/cputype.h>
22#include <mach/irqs.h>
23#include <mach/mfp.h>
24#include <mach/devices.h>
25
26#include "common.h"
27#include "clock.h"
28
29#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
30
31/* APB peripheral clocks */
32static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
33static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
34static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
35static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
36static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
37static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
38static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
39static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
40static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
41static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
42static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
43
44static APMU_CLK(nand, NAND, 0xbf, 100000000);
45
46static struct clk_lookup mmp2_clkregs[] = {
47 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
48 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
49 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
50 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
51 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
52 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
53 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
54 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
55 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
56 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
57 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
58};
59
60static int __init mmp2_init(void)
61{
62 if (cpu_is_mmp2()) {
63 mfp_init_base(MFPR_VIRT_BASE);
64 clks_register(ARRAY_AND_SIZE(mmp2_clkregs));
65 }
66
67 return 0;
68}
69postcore_initcall(mmp2_init);
70
71/* on-chip devices */
72MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
73MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
74MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
75MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
76MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
77MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
78MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
79MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
80MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
81MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
82MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
83
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index a8400bb891e7..cf75694e9687 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -30,7 +30,10 @@
30 30
31#include <mach/addr-map.h> 31#include <mach/addr-map.h>
32#include <mach/regs-timers.h> 32#include <mach/regs-timers.h>
33#include <mach/regs-apbc.h>
33#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <mach/cputype.h>
36#include <asm/mach/time.h>
34 37
35#include "clock.h" 38#include "clock.h"
36 39
@@ -158,7 +161,7 @@ static void __init timer_config(void)
158 161
159 __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ 162 __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
160 163
161 ccr &= TMR_CCR_CS_0(0x3); 164 ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3);
162 __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); 165 __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
163 166
164 /* free-running mode */ 167 /* free-running mode */
@@ -197,3 +200,24 @@ void __init timer_init(int irq)
197 clocksource_register(&cksrc); 200 clocksource_register(&cksrc);
198 clockevents_register_device(&ckevt); 201 clockevents_register_device(&ckevt);
199} 202}
203
204static void __init mmp2_timer_init(void)
205{
206 unsigned long clk_rst;
207
208 __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
209
210 /*
211 * enable bus/functional clock, enable 6.5MHz (divider 4),
212 * release reset
213 */
214 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
215 __raw_writel(clk_rst, APBC_MMP2_TIMERS);
216
217 timer_init(IRQ_MMP2_TIMER1);
218}
219
220struct sys_timer mmp2_timer = {
221 .init = mmp2_timer_init,
222};
223
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 03:17:27 -0500