diff options
author | Chao Xie <chao.xie@marvell.com> | 2012-08-26 22:54:02 -0400 |
---|---|---|
committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-09-08 11:38:19 -0400 |
commit | 8430305dc3f3a286a337f1b4419c04afe55a2583 (patch) | |
tree | e5734fe16407a0b0a71e10cd6943a82466cf84f2 /arch/arm/mach-mmp | |
parent | 9e73d6982314a903beebb2e47e585a9804f237cf (diff) |
ARM: mmp: move mmp2 clock definition to separated file
move mmp2 clock definition to another file. Then mmp2 can
choose common clock framework or private clock framework.
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r-- | arch/arm/mach-mmp/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/clock-mmp2.c | 111 | ||||
-rw-r--r-- | arch/arm/mach-mmp/common.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/mmp2.c | 71 |
4 files changed, 118 insertions, 66 deletions
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index ac0e8858c9d8..095c155d6fb8 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile | |||
@@ -13,6 +13,7 @@ ifeq ($(CONFIG_COMMON_CLK), ) | |||
13 | obj-y += clock.o | 13 | obj-y += clock.o |
14 | obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o | 14 | obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o |
15 | obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o | 15 | obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o |
16 | obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o | ||
16 | endif | 17 | endif |
17 | ifeq ($(CONFIG_PM),y) | 18 | ifeq ($(CONFIG_PM),y) |
18 | obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o | 19 | obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o |
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c new file mode 100644 index 000000000000..21d22002cd19 --- /dev/null +++ b/arch/arm/mach-mmp/clock-mmp2.c | |||
@@ -0,0 +1,111 @@ | |||
1 | #include <linux/module.h> | ||
2 | #include <linux/kernel.h> | ||
3 | #include <linux/init.h> | ||
4 | #include <linux/list.h> | ||
5 | #include <linux/io.h> | ||
6 | #include <linux/clk.h> | ||
7 | |||
8 | #include <mach/addr-map.h> | ||
9 | |||
10 | #include "common.h" | ||
11 | #include "clock.h" | ||
12 | |||
13 | /* | ||
14 | * APB Clock register offsets for MMP2 | ||
15 | */ | ||
16 | #define APBC_RTC APBC_REG(0x000) | ||
17 | #define APBC_TWSI1 APBC_REG(0x004) | ||
18 | #define APBC_TWSI2 APBC_REG(0x008) | ||
19 | #define APBC_TWSI3 APBC_REG(0x00c) | ||
20 | #define APBC_TWSI4 APBC_REG(0x010) | ||
21 | #define APBC_KPC APBC_REG(0x018) | ||
22 | #define APBC_UART1 APBC_REG(0x02c) | ||
23 | #define APBC_UART2 APBC_REG(0x030) | ||
24 | #define APBC_UART3 APBC_REG(0x034) | ||
25 | #define APBC_GPIO APBC_REG(0x038) | ||
26 | #define APBC_PWM0 APBC_REG(0x03c) | ||
27 | #define APBC_PWM1 APBC_REG(0x040) | ||
28 | #define APBC_PWM2 APBC_REG(0x044) | ||
29 | #define APBC_PWM3 APBC_REG(0x048) | ||
30 | #define APBC_SSP0 APBC_REG(0x04c) | ||
31 | #define APBC_SSP1 APBC_REG(0x050) | ||
32 | #define APBC_SSP2 APBC_REG(0x054) | ||
33 | #define APBC_SSP3 APBC_REG(0x058) | ||
34 | #define APBC_SSP4 APBC_REG(0x05c) | ||
35 | #define APBC_SSP5 APBC_REG(0x060) | ||
36 | #define APBC_TWSI5 APBC_REG(0x07c) | ||
37 | #define APBC_TWSI6 APBC_REG(0x080) | ||
38 | #define APBC_UART4 APBC_REG(0x088) | ||
39 | |||
40 | #define APMU_USB APMU_REG(0x05c) | ||
41 | #define APMU_NAND APMU_REG(0x060) | ||
42 | #define APMU_SDH0 APMU_REG(0x054) | ||
43 | #define APMU_SDH1 APMU_REG(0x058) | ||
44 | #define APMU_SDH2 APMU_REG(0x0e8) | ||
45 | #define APMU_SDH3 APMU_REG(0x0ec) | ||
46 | |||
47 | static void sdhc_clk_enable(struct clk *clk) | ||
48 | { | ||
49 | uint32_t clk_rst; | ||
50 | |||
51 | clk_rst = __raw_readl(clk->clk_rst); | ||
52 | clk_rst |= clk->enable_val; | ||
53 | __raw_writel(clk_rst, clk->clk_rst); | ||
54 | } | ||
55 | |||
56 | static void sdhc_clk_disable(struct clk *clk) | ||
57 | { | ||
58 | uint32_t clk_rst; | ||
59 | |||
60 | clk_rst = __raw_readl(clk->clk_rst); | ||
61 | clk_rst &= ~clk->enable_val; | ||
62 | __raw_writel(clk_rst, clk->clk_rst); | ||
63 | } | ||
64 | |||
65 | struct clkops sdhc_clk_ops = { | ||
66 | .enable = sdhc_clk_enable, | ||
67 | .disable = sdhc_clk_disable, | ||
68 | }; | ||
69 | |||
70 | /* APB peripheral clocks */ | ||
71 | static APBC_CLK(uart1, UART1, 1, 26000000); | ||
72 | static APBC_CLK(uart2, UART2, 1, 26000000); | ||
73 | static APBC_CLK(uart3, UART3, 1, 26000000); | ||
74 | static APBC_CLK(uart4, UART4, 1, 26000000); | ||
75 | static APBC_CLK(twsi1, TWSI1, 0, 26000000); | ||
76 | static APBC_CLK(twsi2, TWSI2, 0, 26000000); | ||
77 | static APBC_CLK(twsi3, TWSI3, 0, 26000000); | ||
78 | static APBC_CLK(twsi4, TWSI4, 0, 26000000); | ||
79 | static APBC_CLK(twsi5, TWSI5, 0, 26000000); | ||
80 | static APBC_CLK(twsi6, TWSI6, 0, 26000000); | ||
81 | static APBC_CLK(gpio, GPIO, 0, 26000000); | ||
82 | |||
83 | static APMU_CLK(nand, NAND, 0xbf, 100000000); | ||
84 | static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); | ||
85 | static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); | ||
86 | static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); | ||
87 | static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); | ||
88 | |||
89 | static struct clk_lookup mmp2_clkregs[] = { | ||
90 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
91 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
92 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | ||
93 | INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), | ||
94 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), | ||
95 | INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), | ||
96 | INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), | ||
97 | INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), | ||
98 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), | ||
99 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), | ||
100 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | ||
101 | INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), | ||
102 | INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), | ||
103 | INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), | ||
104 | INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), | ||
105 | INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), | ||
106 | }; | ||
107 | |||
108 | void __init mmp2_clk_init(void) | ||
109 | { | ||
110 | clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); | ||
111 | } | ||
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index 1cad41b41c51..bd453274fca2 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h | |||
@@ -9,3 +9,4 @@ extern void __init mmp_map_io(void); | |||
9 | extern void mmp_restart(char, const char *); | 9 | extern void mmp_restart(char, const char *); |
10 | extern void __init pxa168_clk_init(void); | 10 | extern void __init pxa168_clk_init(void); |
11 | extern void __init pxa910_clk_init(void); | 11 | extern void __init pxa910_clk_init(void); |
12 | extern void __init mmp2_clk_init(void); | ||
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index c709a24a9d25..c2ce3d05b044 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <asm/mach/time.h> | 20 | #include <asm/mach/time.h> |
21 | #include <mach/addr-map.h> | 21 | #include <mach/addr-map.h> |
22 | #include <mach/regs-apbc.h> | 22 | #include <mach/regs-apbc.h> |
23 | #include <mach/regs-apmu.h> | ||
24 | #include <mach/cputype.h> | 23 | #include <mach/cputype.h> |
25 | #include <mach/irqs.h> | 24 | #include <mach/irqs.h> |
26 | #include <mach/dma.h> | 25 | #include <mach/dma.h> |
@@ -29,7 +28,6 @@ | |||
29 | #include <mach/mmp2.h> | 28 | #include <mach/mmp2.h> |
30 | 29 | ||
31 | #include "common.h" | 30 | #include "common.h" |
32 | #include "clock.h" | ||
33 | 31 | ||
34 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | 32 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) |
35 | 33 | ||
@@ -98,67 +96,6 @@ void __init mmp2_init_irq(void) | |||
98 | mmp2_init_icu(); | 96 | mmp2_init_icu(); |
99 | } | 97 | } |
100 | 98 | ||
101 | static void sdhc_clk_enable(struct clk *clk) | ||
102 | { | ||
103 | uint32_t clk_rst; | ||
104 | |||
105 | clk_rst = __raw_readl(clk->clk_rst); | ||
106 | clk_rst |= clk->enable_val; | ||
107 | __raw_writel(clk_rst, clk->clk_rst); | ||
108 | } | ||
109 | |||
110 | static void sdhc_clk_disable(struct clk *clk) | ||
111 | { | ||
112 | uint32_t clk_rst; | ||
113 | |||
114 | clk_rst = __raw_readl(clk->clk_rst); | ||
115 | clk_rst &= ~clk->enable_val; | ||
116 | __raw_writel(clk_rst, clk->clk_rst); | ||
117 | } | ||
118 | |||
119 | struct clkops sdhc_clk_ops = { | ||
120 | .enable = sdhc_clk_enable, | ||
121 | .disable = sdhc_clk_disable, | ||
122 | }; | ||
123 | |||
124 | /* APB peripheral clocks */ | ||
125 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); | ||
126 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); | ||
127 | static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); | ||
128 | static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); | ||
129 | static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); | ||
130 | static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); | ||
131 | static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); | ||
132 | static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); | ||
133 | static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); | ||
134 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); | ||
135 | static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000); | ||
136 | |||
137 | static APMU_CLK(nand, NAND, 0xbf, 100000000); | ||
138 | static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); | ||
139 | static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); | ||
140 | static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); | ||
141 | static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); | ||
142 | |||
143 | static struct clk_lookup mmp2_clkregs[] = { | ||
144 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
145 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
146 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | ||
147 | INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), | ||
148 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), | ||
149 | INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), | ||
150 | INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), | ||
151 | INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), | ||
152 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), | ||
153 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), | ||
154 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | ||
155 | INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), | ||
156 | INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), | ||
157 | INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), | ||
158 | INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), | ||
159 | INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), | ||
160 | }; | ||
161 | |||
162 | static int __init mmp2_init(void) | 99 | static int __init mmp2_init(void) |
163 | { | 100 | { |
164 | if (cpu_is_mmp2()) { | 101 | if (cpu_is_mmp2()) { |
@@ -168,25 +105,27 @@ static int __init mmp2_init(void) | |||
168 | mfp_init_base(MFPR_VIRT_BASE); | 105 | mfp_init_base(MFPR_VIRT_BASE); |
169 | mfp_init_addr(mmp2_addr_map); | 106 | mfp_init_addr(mmp2_addr_map); |
170 | pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); | 107 | pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); |
171 | clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); | 108 | mmp2_clk_init(); |
172 | } | 109 | } |
173 | 110 | ||
174 | return 0; | 111 | return 0; |
175 | } | 112 | } |
176 | postcore_initcall(mmp2_init); | 113 | postcore_initcall(mmp2_init); |
177 | 114 | ||
115 | #define APBC_TIMERS APBC_REG(0x024) | ||
116 | |||
178 | static void __init mmp2_timer_init(void) | 117 | static void __init mmp2_timer_init(void) |
179 | { | 118 | { |
180 | unsigned long clk_rst; | 119 | unsigned long clk_rst; |
181 | 120 | ||
182 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); | 121 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); |
183 | 122 | ||
184 | /* | 123 | /* |
185 | * enable bus/functional clock, enable 6.5MHz (divider 4), | 124 | * enable bus/functional clock, enable 6.5MHz (divider 4), |
186 | * release reset | 125 | * release reset |
187 | */ | 126 | */ |
188 | clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); | 127 | clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); |
189 | __raw_writel(clk_rst, APBC_MMP2_TIMERS); | 128 | __raw_writel(clk_rst, APBC_TIMERS); |
190 | 129 | ||
191 | timer_init(IRQ_MMP2_TIMER1); | 130 | timer_init(IRQ_MMP2_TIMER1); |
192 | } | 131 | } |