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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-15 15:33:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-15 15:33:40 -0500
commit16c1020362083b320868c0deef492249089c3cd3 (patch)
treeff200df3502e6010745713275d69fd0a07e399cf /arch/arm/mach-mmp
parent65e5d002b5ad220db2bf9557f53de5a98f7dab86 (diff)
parentbbba75606963c82febf7bd2761ea848ac5d1a1bb (diff)
Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits) ARM: pxa: fix building issue of missing physmap.h ARM: mmp: PXA910 drive strength FAST using wrong value ARM: mmp: MMP2 drive strength FAST using wrong value ARM: pxa: fix recursive calls in pxa_low_gpio_chip AT91: Support for gsia18s board AT91: Acme Systems FOX Board G20 board files AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h ARM: pxa: fix suspend/resume array index miscalculation ARM: pxa: use cpu_has_ipr() consistently in irq.c ARM: pxa: remove unused variable in clock-pxa3xx.c ARM: pxa: fix warning in zeus.c ARM: sa1111: fix typo in sa1111_retrigger_lowirq() ARM mxs: clkdev related compile fixes ARM i.MX mx31_3ds: Fix MC13783 regulator names ARM: plat-stmp3xxx: irq_data conversion. ARM: plat-spear: irq_data conversion. ARM: plat-orion: irq_data conversion. ARM: plat-omap: irq_data conversion. ARM: plat-nomadik: irq_data conversion. ARM: plat-mxc: irq_data conversion. ... Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert Buytenhek's irq_data conversion clashing with some omap irq updates)
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-mmp2.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa910.h2
-rw-r--r--arch/arm/mach-mmp/irq-mmp2.c46
-rw-r--r--arch/arm/mach-mmp/irq-pxa168.c18
4 files changed, 35 insertions, 33 deletions
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 117e30366087..4ad38629c3f6 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -6,7 +6,7 @@
6#define MFP_DRIVE_VERY_SLOW (0x0 << 13) 6#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
7#define MFP_DRIVE_SLOW (0x2 << 13) 7#define MFP_DRIVE_SLOW (0x2 << 13)
8#define MFP_DRIVE_MEDIUM (0x4 << 13) 8#define MFP_DRIVE_MEDIUM (0x4 << 13)
9#define MFP_DRIVE_FAST (0x8 << 13) 9#define MFP_DRIVE_FAST (0x6 << 13)
10 10
11/* GPIO */ 11/* GPIO */
12#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) 12#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
index 7e8a80f25ddc..fbd7ee8e4897 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -6,7 +6,7 @@
6#define MFP_DRIVE_VERY_SLOW (0x0 << 13) 6#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
7#define MFP_DRIVE_SLOW (0x2 << 13) 7#define MFP_DRIVE_SLOW (0x2 << 13)
8#define MFP_DRIVE_MEDIUM (0x4 << 13) 8#define MFP_DRIVE_MEDIUM (0x4 << 13)
9#define MFP_DRIVE_FAST (0x8 << 13) 9#define MFP_DRIVE_FAST (0x6 << 13)
10 10
11/* UART2 */ 11/* UART2 */
12#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) 12#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
index 01342be91c3c..fa037038e7b8 100644
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -20,48 +20,48 @@
20 20
21#include "common.h" 21#include "common.h"
22 22
23static void icu_mask_irq(unsigned int irq) 23static void icu_mask_irq(struct irq_data *d)
24{ 24{
25 uint32_t r = __raw_readl(ICU_INT_CONF(irq)); 25 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
26 26
27 r &= ~ICU_INT_ROUTE_PJ4_IRQ; 27 r &= ~ICU_INT_ROUTE_PJ4_IRQ;
28 __raw_writel(r, ICU_INT_CONF(irq)); 28 __raw_writel(r, ICU_INT_CONF(d->irq));
29} 29}
30 30
31static void icu_unmask_irq(unsigned int irq) 31static void icu_unmask_irq(struct irq_data *d)
32{ 32{
33 uint32_t r = __raw_readl(ICU_INT_CONF(irq)); 33 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
34 34
35 r |= ICU_INT_ROUTE_PJ4_IRQ; 35 r |= ICU_INT_ROUTE_PJ4_IRQ;
36 __raw_writel(r, ICU_INT_CONF(irq)); 36 __raw_writel(r, ICU_INT_CONF(d->irq));
37} 37}
38 38
39static struct irq_chip icu_irq_chip = { 39static struct irq_chip icu_irq_chip = {
40 .name = "icu_irq", 40 .name = "icu_irq",
41 .mask = icu_mask_irq, 41 .irq_mask = icu_mask_irq,
42 .mask_ack = icu_mask_irq, 42 .irq_mask_ack = icu_mask_irq,
43 .unmask = icu_unmask_irq, 43 .irq_unmask = icu_unmask_irq,
44}; 44};
45 45
46static void pmic_irq_ack(unsigned int irq) 46static void pmic_irq_ack(struct irq_data *d)
47{ 47{
48 if (irq == IRQ_MMP2_PMIC) 48 if (d->irq == IRQ_MMP2_PMIC)
49 mmp2_clear_pmic_int(); 49 mmp2_clear_pmic_int();
50} 50}
51 51
52#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ 52#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
53static void _name_##_mask_irq(unsigned int irq) \ 53static void _name_##_mask_irq(struct irq_data *d) \
54{ \ 54{ \
55 uint32_t r; \ 55 uint32_t r; \
56 r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ 56 r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
57 __raw_writel(r, prefix##_MASK); \ 57 __raw_writel(r, prefix##_MASK); \
58} 58}
59 59
60#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ 60#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
61static void _name_##_unmask_irq(unsigned int irq) \ 61static void _name_##_unmask_irq(struct irq_data *d) \
62{ \ 62{ \
63 uint32_t r; \ 63 uint32_t r; \
64 r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ 64 r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
65 __raw_writel(r, prefix##_MASK); \ 65 __raw_writel(r, prefix##_MASK); \
66} 66}
67 67
@@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
88SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ 88SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
89static struct irq_chip _name_##_irq_chip = { \ 89static struct irq_chip _name_##_irq_chip = { \
90 .name = #_name_, \ 90 .name = #_name_, \
91 .mask = _name_##_mask_irq, \ 91 .irq_mask = _name_##_mask_irq, \
92 .unmask = _name_##_unmask_irq, \ 92 .irq_unmask = _name_##_unmask_irq, \
93} 93}
94 94
95SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); 95SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
@@ -103,10 +103,12 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
103 int irq; 103 int irq;
104 104
105 for (irq = start; num > 0; irq++, num--) { 105 for (irq = start; num > 0; irq++, num--) {
106 struct irq_data *d = irq_get_irq_data(irq);
107
106 /* mask and clear the IRQ */ 108 /* mask and clear the IRQ */
107 chip->mask(irq); 109 chip->irq_mask(d);
108 if (chip->ack) 110 if (chip->irq_ack)
109 chip->ack(irq); 111 chip->irq_ack(d);
110 112
111 set_irq_chip(irq, chip); 113 set_irq_chip(irq, chip);
112 set_irq_flags(irq, IRQF_VALID); 114 set_irq_flags(irq, IRQF_VALID);
@@ -119,7 +121,7 @@ void __init mmp2_init_icu(void)
119 int irq; 121 int irq;
120 122
121 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { 123 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
122 icu_mask_irq(irq); 124 icu_mask_irq(irq_get_irq_data(irq));
123 set_irq_chip(irq, &icu_irq_chip); 125 set_irq_chip(irq, &icu_irq_chip);
124 set_irq_flags(irq, IRQF_VALID); 126 set_irq_flags(irq, IRQF_VALID);
125 127
@@ -139,7 +141,7 @@ void __init mmp2_init_icu(void)
139 /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register 141 /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
140 * to be written to clear the interrupt 142 * to be written to clear the interrupt
141 */ 143 */
142 pmic_irq_chip.ack = pmic_irq_ack; 144 pmic_irq_chip.irq_ack = pmic_irq_ack;
143 145
144 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); 146 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
145 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); 147 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
index 52ff2f065eba..f86b450cb93c 100644
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -25,21 +25,21 @@
25#define PRIORITY_DEFAULT 0x1 25#define PRIORITY_DEFAULT 0x1
26#define PRIORITY_NONE 0x0 /* means IRQ disabled */ 26#define PRIORITY_NONE 0x0 /* means IRQ disabled */
27 27
28static void icu_mask_irq(unsigned int irq) 28static void icu_mask_irq(struct irq_data *d)
29{ 29{
30 __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq)); 30 __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
31} 31}
32 32
33static void icu_unmask_irq(unsigned int irq) 33static void icu_unmask_irq(struct irq_data *d)
34{ 34{
35 __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq)); 35 __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
36} 36}
37 37
38static struct irq_chip icu_irq_chip = { 38static struct irq_chip icu_irq_chip = {
39 .name = "icu_irq", 39 .name = "icu_irq",
40 .ack = icu_mask_irq, 40 .irq_ack = icu_mask_irq,
41 .mask = icu_mask_irq, 41 .irq_mask = icu_mask_irq,
42 .unmask = icu_unmask_irq, 42 .irq_unmask = icu_unmask_irq,
43}; 43};
44 44
45void __init icu_init_irq(void) 45void __init icu_init_irq(void)
@@ -47,7 +47,7 @@ void __init icu_init_irq(void)
47 int irq; 47 int irq;
48 48
49 for (irq = 0; irq < 64; irq++) { 49 for (irq = 0; irq < 64; irq++) {
50 icu_mask_irq(irq); 50 icu_mask_irq(irq_get_irq_data(irq));
51 set_irq_chip(irq, &icu_irq_chip); 51 set_irq_chip(irq, &icu_irq_chip);
52 set_irq_handler(irq, handle_level_irq); 52 set_irq_handler(irq, handle_level_irq);
53 set_irq_flags(irq, IRQF_VALID); 53 set_irq_flags(irq, IRQF_VALID);