[ARM] pxa: add base support for Marvell PXA910

Signed-off-by: Bin Yang <bin.yang@marvell.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>

1 files changed, 158 insertions, 0 deletions

diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
new file mode 100644
index 000000000000..453f8f7758bf
--- /dev/null
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -0,0 +1,158 @@
+/*
+ *  linux/arch/arm/mach-mmp/pxa910.c
+ *
+ *  Code specific to PXA910
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <mach/addr-map.h>
+#include <mach/regs-apbc.h>
+#include <mach/regs-apmu.h>
+#include <mach/cputype.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/dma.h>
+#include <mach/mfp.h>
+#include <mach/devices.h>
+
+#include "common.h"
+#include "clock.h"
+
+#define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
+
+static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
+{
+        MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
+        MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
+        MFP_ADDR_X(GPIO100, GPIO109, 0x238),
+
+        MFP_ADDR(GPIO123, 0xcc),
+        MFP_ADDR(GPIO124, 0xd0),
+
+        MFP_ADDR(DF_IO0, 0x40),
+        MFP_ADDR(DF_IO1, 0x3c),
+        MFP_ADDR(DF_IO2, 0x38),
+        MFP_ADDR(DF_IO3, 0x34),
+        MFP_ADDR(DF_IO4, 0x30),
+        MFP_ADDR(DF_IO5, 0x2c),
+        MFP_ADDR(DF_IO6, 0x28),
+        MFP_ADDR(DF_IO7, 0x24),
+        MFP_ADDR(DF_IO8, 0x20),
+        MFP_ADDR(DF_IO9, 0x1c),
+        MFP_ADDR(DF_IO10, 0x18),
+        MFP_ADDR(DF_IO11, 0x14),
+        MFP_ADDR(DF_IO12, 0x10),
+        MFP_ADDR(DF_IO13, 0xc),
+        MFP_ADDR(DF_IO14, 0x8),
+        MFP_ADDR(DF_IO15, 0x4),
+
+        MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
+        MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
+        MFP_ADDR(SM_nCS0, 0x4c),
+        MFP_ADDR(SM_nCS1, 0x50),
+        MFP_ADDR(DF_WEn, 0x54),
+        MFP_ADDR(DF_REn, 0x58),
+        MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
+        MFP_ADDR(DF_ALE_SM_WEn, 0x60),
+        MFP_ADDR(SM_SCLK, 0x64),
+        MFP_ADDR(DF_RDY0, 0x68),
+        MFP_ADDR(SM_BE0, 0x6c),
+        MFP_ADDR(SM_BE1, 0x70),
+        MFP_ADDR(SM_ADV, 0x74),
+        MFP_ADDR(DF_RDY1, 0x78),
+        MFP_ADDR(SM_ADVMUX, 0x7c),
+        MFP_ADDR(SM_RDY, 0x80),
+
+        MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
+
+        MFP_ADDR_END,
+};
+
+#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
+
+static void __init pxa910_init_gpio(void)
+{
+        int i;
+
+        /* enable GPIO clock */
+        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO);
+
+        /* unmask GPIO edge detection for all 4 banks - APMASKx */
+        for (i = 0; i < 4; i++)
+                __raw_writel(0xffffffff, APMASK(i));
+
+        pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL);
+}
+
+void __init pxa910_init_irq(void)
+{
+        icu_init_irq();
+        pxa910_init_gpio();
+}
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
+static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
+
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+};
+
+static int __init pxa910_init(void)
+{
+        if (cpu_is_pxa910()) {
+                mfp_init_base(MFPR_VIRT_BASE);
+                mfp_init_addr(pxa910_mfp_addr_map);
+                pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
+                clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
+        }
+
+        return 0;
+}
+postcore_initcall(pxa910_init);
+
+/* system timer - clock enabled, 3.25MHz */
+#define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+
+static void __init pxa910_timer_init(void)
+{
+        /* reset and configure */
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
+        __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+
+        timer_init(IRQ_PXA910_AP1_TIMER1);
+}
+
+struct sys_timer pxa910_timer = {
+        .init   = pxa910_timer_init,
+};
+
+/* on-chip devices */
+
+/* NOTE: there are totally 3 UARTs on PXA910:
+ *
+ *   UART1   - Slow UART (can be used both by AP and CP)
+ *   UART2/3 - Fast UART
+ *
+ * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
+ * they are re-ordered as:
+ *
+ *   pxa910_device_uart1 - UART2 as FFUART
+ *   pxa910_device_uart2 - UART3 as BTUART
+ *
+ * UART1 is not used by AP for the moment.
+ */
+PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
+PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);