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authorHaojian Zhuang <haojian.zhuang@marvell.com>2011-10-17 09:26:55 -0400
committerHaojian Zhuang <hzhuang1@hexinfolabs.org>2011-11-15 06:09:36 -0500
commit389eda15e0f41112d7c44213b3c4f8bd1c9398bc (patch)
treed35d07f3d5f1104d6f0ed3dc95a6ded7de72a270 /arch/arm/mach-mmp/mmp2.c
parentbe24168f144122b3730beab257fa058745d14cb4 (diff)
ARM: pxa: add clk support in gpio driver
Support clk in gpio driver. There's no gpio clock in PXA25x and PXA27x. So use dummy clk instead. And move the gpio edge initialization into gpio driver for arch-mmp. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Diffstat (limited to 'arch/arm/mach-mmp/mmp2.c')
-rw-r--r--arch/arm/mach-mmp/mmp2.c11
1 files changed, 2 insertions, 9 deletions
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 1ed222d3e22b..617c60a170a4 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -93,18 +93,9 @@ void mmp2_clear_pmic_int(void)
93 __raw_writel(data, mfpr_pmic); 93 __raw_writel(data, mfpr_pmic);
94} 94}
95 95
96static void __init mmp2_init_gpio(void)
97{
98 int i;
99
100 /* enable GPIO clock */
101 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO);
102}
103
104void __init mmp2_init_irq(void) 96void __init mmp2_init_irq(void)
105{ 97{
106 mmp2_init_icu(); 98 mmp2_init_icu();
107 mmp2_init_gpio();
108} 99}
109 100
110static void sdhc_clk_enable(struct clk *clk) 101static void sdhc_clk_enable(struct clk *clk)
@@ -141,6 +132,7 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
141static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); 132static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
142static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); 133static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
143static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); 134static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
135static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
144 136
145static APMU_CLK(nand, NAND, 0xbf, 100000000); 137static APMU_CLK(nand, NAND, 0xbf, 100000000);
146static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); 138static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
@@ -160,6 +152,7 @@ static struct clk_lookup mmp2_clkregs[] = {
160 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), 152 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
161 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), 153 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
162 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 154 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
155 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
163 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), 156 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
164 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), 157 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
165 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), 158 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),