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authorLinus Torvalds <torvalds@linux-foundation.org>2012-01-09 17:39:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-01-09 17:39:22 -0500
commit2ac9d7aaccbd598b5bd19ac40761b723bb675442 (patch)
tree09132a44e33798aaa5e80f10bf025b510015cab3 /arch/arm/mach-mmp/mmp2.c
parent5ede3ceb7b2c2843e153a1803edbdc8c56655950 (diff)
parentdcf7ec5ee62a78123057a1e286c88ca739717409 (diff)
Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Driver specific changes Again, a lot of platforms have changes in here: pxa, samsung, omap, at91, imx, ... * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) ARM: sa1100: clean up of the clock support ARM: pxa: add dummy clock for sa1100-rtc RTC: sa1100: support sa1100, pxa and mmp soc families RTC: sa1100: remove redundant code of setting alarm RTC: sa1100: Clean out ost register Input: zylonite-wm97xx - replace IRQ_GPIO() with gpio_to_irq() pcmcia: pxa: replace IRQ_GPIO() with gpio_to_irq() ARM: EXYNOS: Modified files for SPI consolidation work ARM: S5P64X0: Enable SDHCI support ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names ARM: S5P64X0: Add HSMMC setup for host Controller ARM: EXYNOS: Add USB OHCI support to ORIGEN board USB: Add Samsung Exynos OHCI diver ARM: EXYNOS: Add USB OHCI support to SMDKV310 board ARM: EXYNOS: Add USB OHCI device net: macb: fix build break with !CONFIG_OF i2c: tegra: Support DVC controller in device tree i2c: tegra: Add __devinit/exit to probe/remove net/at91_ether: use gpio_is_valid for phy IRQ line ARM: at91/net: add macb ethernet controller in 9g45/9g20 DT ...
Diffstat (limited to 'arch/arm/mach-mmp/mmp2.c')
-rw-r--r--arch/arm/mach-mmp/mmp2.c39
1 files changed, 21 insertions, 18 deletions
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 5dd1d4a6aeb9..617c60a170a4 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/platform_device.h>
16 17
17#include <asm/hardware/cache-tauros2.h> 18#include <asm/hardware/cache-tauros2.h>
18 19
@@ -24,7 +25,6 @@
24#include <mach/irqs.h> 25#include <mach/irqs.h>
25#include <mach/dma.h> 26#include <mach/dma.h>
26#include <mach/mfp.h> 27#include <mach/mfp.h>
27#include <mach/gpio-pxa.h>
28#include <mach/devices.h> 28#include <mach/devices.h>
29#include <mach/mmp2.h> 29#include <mach/mmp2.h>
30 30
@@ -33,8 +33,6 @@
33 33
34#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 34#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
35 35
36#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
37
38static struct mfp_addr_map mmp2_addr_map[] __initdata = { 36static struct mfp_addr_map mmp2_addr_map[] __initdata = {
39 37
40 MFP_ADDR_X(GPIO0, GPIO58, 0x54), 38 MFP_ADDR_X(GPIO0, GPIO58, 0x54),
@@ -95,24 +93,9 @@ void mmp2_clear_pmic_int(void)
95 __raw_writel(data, mfpr_pmic); 93 __raw_writel(data, mfpr_pmic);
96} 94}
97 95
98static void __init mmp2_init_gpio(void)
99{
100 int i;
101
102 /* enable GPIO clock */
103 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO);
104
105 /* unmask GPIO edge detection for all 6 banks -- APMASKx */
106 for (i = 0; i < 6; i++)
107 __raw_writel(0xffffffff, APMASK(i));
108
109 pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL);
110}
111
112void __init mmp2_init_irq(void) 96void __init mmp2_init_irq(void)
113{ 97{
114 mmp2_init_icu(); 98 mmp2_init_icu();
115 mmp2_init_gpio();
116} 99}
117 100
118static void sdhc_clk_enable(struct clk *clk) 101static void sdhc_clk_enable(struct clk *clk)
@@ -149,6 +132,7 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
149static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); 132static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
150static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); 133static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
151static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); 134static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
135static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
152 136
153static APMU_CLK(nand, NAND, 0xbf, 100000000); 137static APMU_CLK(nand, NAND, 0xbf, 100000000);
154static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); 138static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
@@ -168,6 +152,7 @@ static struct clk_lookup mmp2_clkregs[] = {
168 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), 152 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
169 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), 153 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
170 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 154 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
155 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
171 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), 156 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
172 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), 157 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
173 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), 158 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
@@ -230,3 +215,21 @@ MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
230/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */ 215/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
231MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000); 216MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
232 217
218struct resource mmp2_resource_gpio[] = {
219 {
220 .start = 0xd4019000,
221 .end = 0xd4019fff,
222 .flags = IORESOURCE_MEM,
223 }, {
224 .start = IRQ_MMP2_GPIO,
225 .end = IRQ_MMP2_GPIO,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230struct platform_device mmp2_device_gpio = {
231 .name = "pxa-gpio",
232 .id = -1,
233 .num_resources = ARRAY_SIZE(mmp2_resource_gpio),
234 .resource = mmp2_resource_gpio,
235};