diff options
author | Eric Miao <eric.miao@marvell.com> | 2009-04-13 06:29:52 -0400 |
---|---|---|
committer | Eric Miao <eric.y.miao@gmail.com> | 2009-06-04 22:32:06 -0400 |
commit | a27ba768a11ac7a1d56688d4224cef3a802d1f89 (patch) | |
tree | b6454495caae2103a104c0ae14232eed6e151738 /arch/arm/mach-mmp/include/mach/regs-apbc.h | |
parent | 2a55b910e0d240984860fa0264866c122751bd09 (diff) |
[ARM] pxa: add PWM devices support for pxa168/910
Signed-off-by: Mingwei Wang <mingwei.wang@marvell.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/regs-apbc.h')
-rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index c6b8c9dc2026..98ccbee4bd0c 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h | |||
@@ -22,8 +22,10 @@ | |||
22 | #define APBC_PXA168_UART1 APBC_REG(0x000) | 22 | #define APBC_PXA168_UART1 APBC_REG(0x000) |
23 | #define APBC_PXA168_UART2 APBC_REG(0x004) | 23 | #define APBC_PXA168_UART2 APBC_REG(0x004) |
24 | #define APBC_PXA168_GPIO APBC_REG(0x008) | 24 | #define APBC_PXA168_GPIO APBC_REG(0x008) |
25 | #define APBC_PXA168_PWM0 APBC_REG(0x00c) | 25 | #define APBC_PXA168_PWM1 APBC_REG(0x00c) |
26 | #define APBC_PXA168_PWM1 APBC_REG(0x010) | 26 | #define APBC_PXA168_PWM2 APBC_REG(0x010) |
27 | #define APBC_PXA168_PWM3 APBC_REG(0x014) | ||
28 | #define APBC_PXA168_PWM4 APBC_REG(0x018) | ||
27 | #define APBC_PXA168_SSP1 APBC_REG(0x01c) | 29 | #define APBC_PXA168_SSP1 APBC_REG(0x01c) |
28 | #define APBC_PXA168_SSP2 APBC_REG(0x020) | 30 | #define APBC_PXA168_SSP2 APBC_REG(0x020) |
29 | #define APBC_PXA168_RTC APBC_REG(0x028) | 31 | #define APBC_PXA168_RTC APBC_REG(0x028) |
@@ -48,10 +50,10 @@ | |||
48 | #define APBC_PXA910_UART0 APBC_REG(0x000) | 50 | #define APBC_PXA910_UART0 APBC_REG(0x000) |
49 | #define APBC_PXA910_UART1 APBC_REG(0x004) | 51 | #define APBC_PXA910_UART1 APBC_REG(0x004) |
50 | #define APBC_PXA910_GPIO APBC_REG(0x008) | 52 | #define APBC_PXA910_GPIO APBC_REG(0x008) |
51 | #define APBC_PXA910_PWM0 APBC_REG(0x00c) | 53 | #define APBC_PXA910_PWM1 APBC_REG(0x00c) |
52 | #define APBC_PXA910_PWM1 APBC_REG(0x010) | 54 | #define APBC_PXA910_PWM2 APBC_REG(0x010) |
53 | #define APBC_PXA910_PWM2 APBC_REG(0x014) | 55 | #define APBC_PXA910_PWM3 APBC_REG(0x014) |
54 | #define APBC_PXA910_PWM3 APBC_REG(0x018) | 56 | #define APBC_PXA910_PWM4 APBC_REG(0x018) |
55 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) | 57 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) |
56 | #define APBC_PXA910_SSP2 APBC_REG(0x020) | 58 | #define APBC_PXA910_SSP2 APBC_REG(0x020) |
57 | #define APBC_PXA910_IPC APBC_REG(0x024) | 59 | #define APBC_PXA910_IPC APBC_REG(0x024) |