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authorEric Miao <eric.miao@marvell.com>2009-01-20 04:20:56 -0500
committerEric Miao <eric.miao@marvell.com>2009-03-22 22:11:34 -0400
commita7a89d9621ba877ae45784cf7d000182075df9c1 (patch)
treea6baf058a43f72088750af59c3d78ee3f512a69d /arch/arm/mach-mmp/include/mach/mfp.h
parente2bb6650ef94c64723e2dd35ab92410b9477bc64 (diff)
[ARM] pxa: add MFP support for pxa168
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/mfp.h')
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h
new file mode 100644
index 000000000000..277ea4cd0f9f
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp.h
@@ -0,0 +1,37 @@
1#ifndef __ASM_MACH_MFP_H
2#define __ASM_MACH_MFP_H
3
4#include <plat/mfp.h>
5
6/*
7 * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
8 * bit different from those on PXA3xx. Bit [7:10] are now reserved, which
9 * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
10 *
11 * To cope with this difference and re-use the pxa3xx mfp code as much as
12 * possible, we make the following compromise:
13 *
14 * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
15 * 2. DRIVE strength definitions redefined to include the reserved bit10
16 * 3. Override MFP_CFG() and MFP_CFG_DRV()
17 * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
18 */
19
20#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
21#define MFP_DRIVE_SLOW (0x2 << 13)
22#define MFP_DRIVE_MEDIUM (0x4 << 13)
23#define MFP_DRIVE_FAST (0x8 << 13)
24
25#undef MFP_CFG
26#undef MFP_CFG_DRV
27#undef MFP_CFG_LPM
28#undef MFP_CFG_X
29#undef MFP_CFG_DEFAULT
30
31#define MFP_CFG(pin, af) \
32 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
33
34#define MFP_CFG_DRV(pin, af, drv) \
35 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
36
37#endif /* __ASM_MACH_MFP_H */