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authorHaojian Zhuang <haojian.zhuang@marvell.com>2009-12-04 09:41:28 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-03-01 18:40:55 -0500
commit2f7e8faef5a50efaa1c173e99bdaa29e0129bb99 (patch)
treec73ae01004e110a87b7cf6cae686b9c142e2a63b /arch/arm/mach-mmp/include/mach/entry-macro.S
parent978da5bcdb33f6e030fa3304662e2455a018f1b0 (diff)
[ARM] mmp: add support for Marvell MMP2
Marvell MMP2 (aka ARMADA610) is a SoC based on PJ4 core. It's ARMv6 compatible. Support basic interrupt handler and timer, and basic support for MMP2 based FLINT platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/entry-macro.S')
-rw-r--r--arch/arm/mach-mmp/include/mach/entry-macro.S7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 6d3cd35478b5..c42d9d4e892d 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -15,7 +15,12 @@
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =ICU_AP_IRQ_SEL_INT_NUM 18 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
19 and \tmp, \tmp, #0xff00
20 cmp \tmp, #0x5800
21 ldr \base, =ICU_VIRT_BASE
22 addne \base, \base, #0x10c @ PJ1 AP INT SEL register
23 addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
19 .endm 24 .endm
20 25
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp