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authorRoland Stigge <stigge@antcom.de>2012-06-14 10:16:17 -0400
committerRoland Stigge <stigge@antcom.de>2012-06-14 10:16:17 -0400
commit291dd71fe48c0b696a9391ed1ba476c8878d6fca (patch)
treece8eab4cff1ee6040018b612d45eddd4f9b91e1a /arch/arm/mach-lpc32xx
parent360c9627cc3b0334514d6cb8260833e768c71b63 (diff)
ARM: LPC32xx: Add MMC controller support
This patch adds support for the MMC controller of the LPC32xx SoC to the platform initialization via the pl08x primecell driver. Lacking more complete DT support, done via DT auxdata. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c43
1 files changed, 39 insertions, 4 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index eade77fbebdd..03ee3491b7cf 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -30,12 +30,13 @@
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h> 31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h> 32#include <linux/amba/pl022.h>
33#include <linux/amba/pl08x.h>
34#include <linux/amba/mmci.h>
33#include <linux/of.h> 35#include <linux/of.h>
34#include <linux/of_address.h> 36#include <linux/of_address.h>
35#include <linux/of_irq.h> 37#include <linux/of_irq.h>
36#include <linux/of_platform.h> 38#include <linux/of_platform.h>
37#include <linux/clk.h> 39#include <linux/clk.h>
38#include <linux/amba/pl08x.h>
39 40
40#include <asm/setup.h> 41#include <asm/setup.h>
41#include <asm/mach-types.h> 42#include <asm/mach-types.h>
@@ -50,9 +51,12 @@
50/* 51/*
51 * Mapped GPIOLIB GPIOs 52 * Mapped GPIOLIB GPIOs
52 */ 53 */
53#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) 54#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) 55#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) 56#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
57#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
58#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
59#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
56 60
57/* 61/*
58 * AMBA LCD controller 62 * AMBA LCD controller
@@ -260,11 +264,32 @@ static struct pl08x_platform_data pl08x_pd = {
260 .mem_buses = PL08X_AHB1, 264 .mem_buses = PL08X_AHB1,
261}; 265};
262 266
267static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
268{
269 /* Only on and off are supported */
270 if (ios->power_mode == MMC_POWER_OFF)
271 gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
272 else
273 gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
274 return 0;
275}
276
277static struct mmci_platform_data lpc32xx_mmci_data = {
278 .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
279 MMC_VDD_32_33 | MMC_VDD_33_34,
280 .ios_handler = mmc_handle_ios,
281 .dma_filter = NULL,
282 /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
283 * gather, and the MMCI driver doesn't do it this way */
284};
285
263static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { 286static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
264 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data), 287 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
265 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), 288 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
266 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), 289 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
267 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), 290 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
291 OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
292 &lpc32xx_mmci_data),
268 { } 293 { }
269}; 294};
270 295
@@ -308,6 +333,11 @@ static void __init lpc3250_machine_init(void)
308 * detection or a data fault will occur, so enable the clocks 333 * detection or a data fault will occur, so enable the clocks
309 * here. 334 * here.
310 */ 335 */
336 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
337 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
338 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
339 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
340
311 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); 341 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
312 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), 342 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
313 LPC32XX_CLKPWR_LCDCLK_CTRL); 343 LPC32XX_CLKPWR_LCDCLK_CTRL);
@@ -335,6 +365,11 @@ static void __init lpc3250_machine_init(void)
335 else if (gpio_direction_output(SPI0_CS_GPIO, 1)) 365 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
336 printk(KERN_ERR "Error setting gpio %u to output", 366 printk(KERN_ERR "Error setting gpio %u to output",
337 SPI0_CS_GPIO); 367 SPI0_CS_GPIO);
368
369 if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
370 pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
371 else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
372 pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
338} 373}
339 374
340static char const *lpc32xx_dt_compat[] __initdata = { 375static char const *lpc32xx_dt_compat[] __initdata = {