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authorRoland Stigge <stigge@antcom.de>2012-07-01 15:06:44 -0400
committerRoland Stigge <stigge@antcom.de>2012-07-01 15:06:44 -0400
commit5df5d01dd04ce0dde58e305dd258c7e54f079e65 (patch)
tree4f2bb93f12b64e2039e1c8f1287402a0057b1f22 /arch/arm/mach-lpc32xx
parentdf072717eb0050326f0f63eed98200412c395831 (diff)
ARM: LPC32xx: Init MMC via clock
This patch moves MMC/SD controller initialization from the board specific file phy3250.c to clock.c. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r--arch/arm/mach-lpc32xx/clock.c6
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c5
2 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index e8d315e6db09..345c28d5615b 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -812,11 +812,13 @@ static int mmc_onoff_enable(struct clk *clk, int enable)
812 u32 tmp; 812 u32 tmp;
813 813
814 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & 814 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
815 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; 815 ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
816 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN);
816 817
817 /* If rate is 0, disable clock */ 818 /* If rate is 0, disable clock */
818 if (enable != 0) 819 if (enable != 0)
819 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; 820 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
821 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
820 822
821 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); 823 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
822 824
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index c1aabfcbde49..5be2cbfb4d99 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -262,11 +262,6 @@ static void __init lpc3250_machine_init(void)
262 262
263 lpc32xx_serial_init(); 263 lpc32xx_serial_init();
264 264
265 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
266 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
267 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
268 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
269
270 /* Test clock needed for UDA1380 initial init */ 265 /* Test clock needed for UDA1380 initial init */
271 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | 266 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
272 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, 267 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,