diff options
author | Alexandre Pereira da Silva <aletes.xgr@gmail.com> | 2012-06-13 18:28:23 -0400 |
---|---|---|
committer | Roland Stigge <stigge@antcom.de> | 2012-06-14 10:16:19 -0400 |
commit | 112e9adda4ddcd56895f20c4c886d2493d7907f3 (patch) | |
tree | 123c1790ac66b737307237d1201db0932b2b4d40 /arch/arm/mach-lpc32xx | |
parent | 72b78cf713176f376f369df8ccca865c5d51c42b (diff) |
ARM: LPC32xx: Cleanup board init, remove duplicate clock init
Remove SSP0, CLCD and DMA clocks that are already migrated to
the clock framework.
Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r-- | arch/arm/mach-lpc32xx/phy3250.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 93408883eaca..d7389598c21a 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c | |||
@@ -272,28 +272,11 @@ static void __init lpc3250_machine_init(void) | |||
272 | 272 | ||
273 | lpc32xx_serial_init(); | 273 | lpc32xx_serial_init(); |
274 | 274 | ||
275 | /* | ||
276 | * AMBA peripheral clocks need to be enabled prior to AMBA device | ||
277 | * detection or a data fault will occur, so enable the clocks | ||
278 | * here. | ||
279 | */ | ||
280 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); | 275 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); |
281 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | | 276 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | |
282 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; | 277 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; |
283 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); | 278 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); |
284 | 279 | ||
285 | tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); | ||
286 | __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), | ||
287 | LPC32XX_CLKPWR_LCDCLK_CTRL); | ||
288 | |||
289 | tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); | ||
290 | __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), | ||
291 | LPC32XX_CLKPWR_SSP_CLK_CTRL); | ||
292 | |||
293 | tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL); | ||
294 | __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN), | ||
295 | LPC32XX_CLKPWR_DMA_CLK_CTRL); | ||
296 | |||
297 | /* Test clock needed for UDA1380 initial init */ | 280 | /* Test clock needed for UDA1380 initial init */ |
298 | __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | | 281 | __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | |
299 | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, | 282 | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, |