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authorJames Morris <jmorris@namei.org>2011-04-19 07:32:41 -0400
committerJames Morris <jmorris@namei.org>2011-04-19 07:32:41 -0400
commitd4ab4e6a23f805abb8fc3cc34525eec3788aeca1 (patch)
treeeefd82c155bc27469a85667d759cd90facf4a6e3 /arch/arm/mach-lpc32xx/pm.c
parentc0fa797ae6cd02ff87c0bfe0d509368a3b45640e (diff)
parent96fd2d57b8252e16dfacf8941f7a74a6119197f5 (diff)
Merge branch 'master'; commit 'v2.6.39-rc3' into next
Diffstat (limited to 'arch/arm/mach-lpc32xx/pm.c')
-rw-r--r--arch/arm/mach-lpc32xx/pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index e76d41bb7056..b9c80597b7bf 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -41,7 +41,7 @@
41 * DRAM clocking and refresh are slightly different for systems with DDR 41 * DRAM clocking and refresh are slightly different for systems with DDR
42 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the 42 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems, 43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transistion to direct-run mode will stop all DDR accesses (no clocks). 44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
45 * Because of this, the code to switch power modes and the code to enter 45 * Because of this, the code to switch power modes and the code to enter
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small 46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
47 * section of IRAM is used instead for this. 47 * section of IRAM is used instead for this.