diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2010-11-29 04:35:20 -0500 |
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committer | Lennert Buytenhek <buytenh@wantstofly.org> | 2011-01-13 11:18:44 -0500 |
commit | 5638538117ea81063b0611a7374c0d65133860ec (patch) | |
tree | 623313bfca0b99f5d8b975ffef79df7962fcd47a /arch/arm/mach-lpc32xx/irq.c | |
parent | 3b7cff6604768bd561b032a02c38746707cbd3d1 (diff) |
ARM: lpc32xx: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Diffstat (limited to 'arch/arm/mach-lpc32xx/irq.c')
-rw-r--r-- | arch/arm/mach-lpc32xx/irq.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index bd0df26c415b..316ecbf6c586 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c | |||
@@ -191,38 +191,38 @@ static void get_controller(unsigned int irq, unsigned int *base, | |||
191 | } | 191 | } |
192 | } | 192 | } |
193 | 193 | ||
194 | static void lpc32xx_mask_irq(unsigned int irq) | 194 | static void lpc32xx_mask_irq(struct irq_data *d) |
195 | { | 195 | { |
196 | unsigned int reg, ctrl, mask; | 196 | unsigned int reg, ctrl, mask; |
197 | 197 | ||
198 | get_controller(irq, &ctrl, &mask); | 198 | get_controller(d->irq, &ctrl, &mask); |
199 | 199 | ||
200 | reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; | 200 | reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; |
201 | __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); | 201 | __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); |
202 | } | 202 | } |
203 | 203 | ||
204 | static void lpc32xx_unmask_irq(unsigned int irq) | 204 | static void lpc32xx_unmask_irq(struct irq_data *d) |
205 | { | 205 | { |
206 | unsigned int reg, ctrl, mask; | 206 | unsigned int reg, ctrl, mask; |
207 | 207 | ||
208 | get_controller(irq, &ctrl, &mask); | 208 | get_controller(d->irq, &ctrl, &mask); |
209 | 209 | ||
210 | reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; | 210 | reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; |
211 | __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); | 211 | __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); |
212 | } | 212 | } |
213 | 213 | ||
214 | static void lpc32xx_ack_irq(unsigned int irq) | 214 | static void lpc32xx_ack_irq(struct irq_data *d) |
215 | { | 215 | { |
216 | unsigned int ctrl, mask; | 216 | unsigned int ctrl, mask; |
217 | 217 | ||
218 | get_controller(irq, &ctrl, &mask); | 218 | get_controller(d->irq, &ctrl, &mask); |
219 | 219 | ||
220 | __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); | 220 | __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); |
221 | 221 | ||
222 | /* Also need to clear pending wake event */ | 222 | /* Also need to clear pending wake event */ |
223 | if (lpc32xx_events[irq].mask != 0) | 223 | if (lpc32xx_events[d->irq].mask != 0) |
224 | __raw_writel(lpc32xx_events[irq].mask, | 224 | __raw_writel(lpc32xx_events[d->irq].mask, |
225 | lpc32xx_events[irq].event_group->rawstat_reg); | 225 | lpc32xx_events[d->irq].event_group->rawstat_reg); |
226 | } | 226 | } |
227 | 227 | ||
228 | static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, | 228 | static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, |
@@ -261,27 +261,27 @@ static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, | |||
261 | } | 261 | } |
262 | } | 262 | } |
263 | 263 | ||
264 | static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) | 264 | static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) |
265 | { | 265 | { |
266 | switch (type) { | 266 | switch (type) { |
267 | case IRQ_TYPE_EDGE_RISING: | 267 | case IRQ_TYPE_EDGE_RISING: |
268 | /* Rising edge sensitive */ | 268 | /* Rising edge sensitive */ |
269 | __lpc32xx_set_irq_type(irq, 1, 1); | 269 | __lpc32xx_set_irq_type(d->irq, 1, 1); |
270 | break; | 270 | break; |
271 | 271 | ||
272 | case IRQ_TYPE_EDGE_FALLING: | 272 | case IRQ_TYPE_EDGE_FALLING: |
273 | /* Falling edge sensitive */ | 273 | /* Falling edge sensitive */ |
274 | __lpc32xx_set_irq_type(irq, 0, 1); | 274 | __lpc32xx_set_irq_type(d->irq, 0, 1); |
275 | break; | 275 | break; |
276 | 276 | ||
277 | case IRQ_TYPE_LEVEL_LOW: | 277 | case IRQ_TYPE_LEVEL_LOW: |
278 | /* Low level sensitive */ | 278 | /* Low level sensitive */ |
279 | __lpc32xx_set_irq_type(irq, 0, 0); | 279 | __lpc32xx_set_irq_type(d->irq, 0, 0); |
280 | break; | 280 | break; |
281 | 281 | ||
282 | case IRQ_TYPE_LEVEL_HIGH: | 282 | case IRQ_TYPE_LEVEL_HIGH: |
283 | /* High level sensitive */ | 283 | /* High level sensitive */ |
284 | __lpc32xx_set_irq_type(irq, 1, 0); | 284 | __lpc32xx_set_irq_type(d->irq, 1, 0); |
285 | break; | 285 | break; |
286 | 286 | ||
287 | /* Other modes are not supported */ | 287 | /* Other modes are not supported */ |
@@ -290,33 +290,33 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) | |||
290 | } | 290 | } |
291 | 291 | ||
292 | /* Ok to use the level handler for all types */ | 292 | /* Ok to use the level handler for all types */ |
293 | set_irq_handler(irq, handle_level_irq); | 293 | set_irq_handler(d->irq, handle_level_irq); |
294 | 294 | ||
295 | return 0; | 295 | return 0; |
296 | } | 296 | } |
297 | 297 | ||
298 | static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state) | 298 | static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) |
299 | { | 299 | { |
300 | unsigned long eventreg; | 300 | unsigned long eventreg; |
301 | 301 | ||
302 | if (lpc32xx_events[irqno].mask != 0) { | 302 | if (lpc32xx_events[d->irq].mask != 0) { |
303 | eventreg = __raw_readl(lpc32xx_events[irqno]. | 303 | eventreg = __raw_readl(lpc32xx_events[d->irq]. |
304 | event_group->enab_reg); | 304 | event_group->enab_reg); |
305 | 305 | ||
306 | if (state) | 306 | if (state) |
307 | eventreg |= lpc32xx_events[irqno].mask; | 307 | eventreg |= lpc32xx_events[d->irq].mask; |
308 | else | 308 | else |
309 | eventreg &= ~lpc32xx_events[irqno].mask; | 309 | eventreg &= ~lpc32xx_events[d->irq].mask; |
310 | 310 | ||
311 | __raw_writel(eventreg, | 311 | __raw_writel(eventreg, |
312 | lpc32xx_events[irqno].event_group->enab_reg); | 312 | lpc32xx_events[d->irq].event_group->enab_reg); |
313 | 313 | ||
314 | return 0; | 314 | return 0; |
315 | } | 315 | } |
316 | 316 | ||
317 | /* Clear event */ | 317 | /* Clear event */ |
318 | __raw_writel(lpc32xx_events[irqno].mask, | 318 | __raw_writel(lpc32xx_events[d->irq].mask, |
319 | lpc32xx_events[irqno].event_group->rawstat_reg); | 319 | lpc32xx_events[d->irq].event_group->rawstat_reg); |
320 | 320 | ||
321 | return -ENODEV; | 321 | return -ENODEV; |
322 | } | 322 | } |
@@ -336,11 +336,11 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr, | |||
336 | } | 336 | } |
337 | 337 | ||
338 | static struct irq_chip lpc32xx_irq_chip = { | 338 | static struct irq_chip lpc32xx_irq_chip = { |
339 | .ack = lpc32xx_ack_irq, | 339 | .irq_ack = lpc32xx_ack_irq, |
340 | .mask = lpc32xx_mask_irq, | 340 | .irq_mask = lpc32xx_mask_irq, |
341 | .unmask = lpc32xx_unmask_irq, | 341 | .irq_unmask = lpc32xx_unmask_irq, |
342 | .set_type = lpc32xx_set_irq_type, | 342 | .irq_set_type = lpc32xx_set_irq_type, |
343 | .set_wake = lpc32xx_irq_wake | 343 | .irq_set_wake = lpc32xx_irq_wake |
344 | }; | 344 | }; |
345 | 345 | ||
346 | static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) | 346 | static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) |