aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-lpc32xx/common.c
diff options
context:
space:
mode:
authorRoland Stigge <stigge@antcom.de>2014-09-09 09:13:14 -0400
committerArnd Bergmann <arnd@arndb.de>2014-09-10 11:25:14 -0400
commit01100c022df5d9b8ac56d3705e33e69dc012a6e2 (patch)
tree28b91fead017b35b735b995c7ada4146e1ce7859 /arch/arm/mach-lpc32xx/common.c
parent8013e8c7117d9d54e84d80480b105f80603d9945 (diff)
ARM: LPC32xx: Fix reset function
In the recent change to the reset function API (commit 7b6d864b48d95e6ea1df7df64475b9cb9616dcf9), the mode argument changed from a char to an enum. lpc23xx_restart() only handles REBOOT_SOFT and REBOOT_HARD, but the new kernel code emits REBOOT_COLD (0) on reboots now which leads to lpc32xx simply not rebooting (but halting). This patch fixes this by just resetting unconditionally as on other platforms (e.g. mach-bcm2835). Pulling lpc32xx_watchdog_reset() into lpc23xx_restart() since the while() in lpc23xx_restart() is part of the procedure anyway and lpc32xx_watchdog_reset() isn't used anywhere else anymore. Signed-off-by: Roland Stigge <stigge@antcom.de>
Diffstat (limited to 'arch/arm/mach-lpc32xx/common.c')
-rw-r--r--arch/arm/mach-lpc32xx/common.c29
1 files changed, 6 insertions, 23 deletions
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index de03620d7fa7..716e83eb1db8 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -57,20 +57,6 @@ int clk_is_sysclk_mainosc(void)
57} 57}
58 58
59/* 59/*
60 * System reset via the watchdog timer
61 */
62static void lpc32xx_watchdog_reset(void)
63{
64 /* Make sure WDT clocks are enabled */
65 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
66 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
67
68 /* Instant assert of RESETOUT_N with pulse length 1mS */
69 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
70 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
71}
72
73/*
74 * Detects and returns IRAM size for the device variation 60 * Detects and returns IRAM size for the device variation
75 */ 61 */
76#define LPC32XX_IRAM_BANK_SIZE SZ_128K 62#define LPC32XX_IRAM_BANK_SIZE SZ_128K
@@ -210,16 +196,13 @@ void __init lpc32xx_map_io(void)
210 196
211void lpc23xx_restart(enum reboot_mode mode, const char *cmd) 197void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
212{ 198{
213 switch (mode) { 199 /* Make sure WDT clocks are enabled */
214 case REBOOT_SOFT: 200 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
215 case REBOOT_HARD: 201 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
216 lpc32xx_watchdog_reset();
217 break;
218 202
219 default: 203 /* Instant assert of RESETOUT_N with pulse length 1mS */
220 /* Do nothing */ 204 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
221 break; 205 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
222 }
223 206
224 /* Wait for watchdog to reset system */ 207 /* Wait for watchdog to reset system */
225 while (1) 208 while (1)