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authorRoland Stigge <stigge@antcom.de>2012-03-13 16:15:40 -0400
committerRoland Stigge <stigge@antcom.de>2012-03-13 16:15:40 -0400
commita7e4c6a7145ee375a688e1701ae4c975d6c6419a (patch)
tree0438b5b99a88ec694bb5a91c8ca0cb52fec928f1 /arch/arm/mach-lpc32xx/clock.c
parent73d43d00649985cf6509b4f99a720665f1b7c559 (diff)
parent678a0222edc9da43a22145d68647500ee85e6c04 (diff)
Merge branch 'lpc32xx/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into lpc32xx/tmp
Conflicts: arch/arm/mach-lpc32xx/clock.c
Diffstat (limited to 'arch/arm/mach-lpc32xx/clock.c')
-rw-r--r--arch/arm/mach-lpc32xx/clock.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 0e01bf44479c..ab8c21647422 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -721,6 +721,41 @@ static struct clk clk_tsc = {
721 .get_rate = local_return_parent_rate, 721 .get_rate = local_return_parent_rate,
722}; 722};
723 723
724static int adc_onoff_enable(struct clk *clk, int enable)
725{
726 u32 tmp;
727 u32 divider;
728
729 /* Use PERIPH_CLOCK */
730 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
731 tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
732 /*
733 * Set clock divider so that we have equal to or less than
734 * 4.5MHz clock at ADC
735 */
736 divider = clk->get_rate(clk) / 4500000 + 1;
737 tmp |= divider;
738 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
739
740 /* synchronize rate of this clock w/ actual HW setting */
741 clk->rate = clk->get_rate(clk->parent) / divider;
742
743 if (enable == 0)
744 __raw_writel(0, clk->enable_reg);
745 else
746 __raw_writel(clk->enable_mask, clk->enable_reg);
747
748 return 0;
749}
750
751static struct clk clk_adc = {
752 .parent = &clk_pclk,
753 .enable = adc_onoff_enable,
754 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
755 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
756 .get_rate = local_return_parent_rate,
757};
758
724static int mmc_onoff_enable(struct clk *clk, int enable) 759static int mmc_onoff_enable(struct clk *clk, int enable)
725{ 760{
726 u32 tmp; 761 u32 tmp;
@@ -1057,6 +1092,7 @@ static struct clk_lookup lookups[] = {
1057 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) 1092 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1058 _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0) 1093 _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
1059 _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1) 1094 _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
1095 _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
1060 _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc) 1096 _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
1061 _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc) 1097 _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
1062 _REGISTER_CLOCK("lpc-net.0", NULL, clk_net) 1098 _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)