[ARM] mm: allow LH7A40x to use sparsemem

Enable Sparsemem support for LH7A40x SoCs, while still allowing the
existing discontig support for the time being.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 12 insertions, 7 deletions

diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig
index 6f4c6a1798c1..9be7466e346c 100644
--- a/arch/arm/mach-lh7a40x/Kconfig
+++ b/arch/arm/mach-lh7a40x/Kconfig
@@ -40,23 +40,22 @@ config LPD7A40X_CPLD_SSP
         bool
 
 config LH7A40X_CONTIGMEM
-        bool "Disable NUMA Support"
-        depends on ARCH_LH7A40X
+        bool "Disable NUMA/SparseMEM Support"
         help
           Say Y here if your bootloader sets the SROMLL bit(s) in
           the SDRAM controller, organizing memory as a contiguous
-          array.  This option will disable CONFIG_DISCONTIGMEM and
-          force the kernel to manage all memory in one node.
+          array.  This option will disable sparse memory support
+          and force the kernel to manage all memory in one node.
 
-          Setting this option incorrectly may prevent the kernel from
-          booting.  It is OK to leave it N.
+          Setting this option incorrectly may prevent the kernel
+          from booting.  It is OK to leave it N.
 
           For more information, consult
             <file:Documentation/arm/Sharp-LH/SDRAM>.
 
 config LH7A40X_ONE_BANK_PER_NODE
         bool "Optimize NUMA Node Tables for Size"
-        depends on ARCH_LH7A40X && !LH7A40X_CONTIGMEM
+        depends on !LH7A40X_CONTIGMEM
         help
           Say Y here to produce compact memory node tables.  By
           default pairs of adjacent physical RAM banks are managed
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
index f7107b4c197a..1da14ff66c93 100644
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -73,4 +73,10 @@
 
 #endif
 
+/*
+ * Sparsemem version of the above
+ */
+#define MAX_PHYSMEM_BITS        32
+#define SECTION_SIZE_BITS       24
+
 #endif