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authorAndrew Lunn <andrew@lunn.ch>2011-12-07 15:48:05 -0500
committerNicolas Pitre <nico@fluxnic.net>2011-12-13 18:46:20 -0500
commitb6d1c33a31deb1784c1d34070db6e84fd6f9d870 (patch)
tree18739a6c79b10f0fe69c01be5571e7a5af4d0e21 /arch/arm/mach-kirkwood
parent527ef0550d79e3b3a0ef8f5061072075afef6aaf (diff)
ARM: Orion: Consolidate the address map setup
Compile tested on Dove, orion5x, mv78xx0. Boot tested on Kirkwood. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Michael Walle <michael@walle.cc> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Diffstat (limited to 'arch/arm/mach-kirkwood')
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c138
1 files changed, 39 insertions, 99 deletions
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 8d03bcef5182..935392f7e13f 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -13,12 +13,12 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/hardware.h> 15#include <mach/hardware.h>
16#include <plat/addr-map.h>
16#include "common.h" 17#include "common.h"
17 18
18/* 19/*
19 * Generic Address Decode Windows bit settings 20 * Generic Address Decode Windows bit settings
20 */ 21 */
21#define TARGET_DDR 0
22#define TARGET_DEV_BUS 1 22#define TARGET_DEV_BUS 1
23#define TARGET_SRAM 3 23#define TARGET_SRAM 3
24#define TARGET_PCIE 4 24#define TARGET_PCIE 4
@@ -35,119 +35,59 @@
35#define ATTR_PCIE1_MEM 0xd8 35#define ATTR_PCIE1_MEM 0xd8
36#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
37 37
38/* 38struct mbus_dram_target_info kirkwood_mbus_dram_info;
39 * Helpers to get DDR bank info
40 */
41#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
42#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
43 39
44/* 40/*
45 * CPU Address Decode Windows registers 41 * Description of the windows needed by the platform code
46 */ 42 */
47#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) 43static struct __initdata orion_addr_map_cfg addr_map_cfg = {
48#define WIN_CTRL_OFF 0x0000 44 .num_wins = 8,
49#define WIN_BASE_OFF 0x0004 45 .remappable_wins = 4,
50#define WIN_REMAP_LO_OFF 0x0008 46 .bridge_virt_base = BRIDGE_VIRT_BASE,
51#define WIN_REMAP_HI_OFF 0x000c 47};
52
53
54struct mbus_dram_target_info kirkwood_mbus_dram_info;
55
56static int __init cpu_win_can_remap(int win)
57{
58 if (win < 4)
59 return 1;
60
61 return 0;
62}
63
64static void __init setup_cpu_win(int win, u32 base, u32 size,
65 u8 target, u8 attr, int remap)
66{
67 void __iomem *addr = (void __iomem *)WIN_OFF(win);
68 u32 ctrl;
69
70 base &= 0xffff0000;
71 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
72
73 writel(base, addr + WIN_BASE_OFF);
74 writel(ctrl, addr + WIN_CTRL_OFF);
75 if (cpu_win_can_remap(win)) {
76 if (remap < 0)
77 remap = base;
78
79 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
80 writel(0, addr + WIN_REMAP_HI_OFF);
81 }
82}
83
84void __init kirkwood_setup_cpu_mbus(void)
85{
86 void __iomem *addr;
87 int i;
88 int cs;
89 48
49static const struct __initdata orion_addr_map_info addr_map_info[] = {
90 /* 50 /*
91 * First, disable and clear windows. 51 * Windows for PCIe IO+MEM space.
92 */ 52 */
93 for (i = 0; i < 8; i++) { 53 { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
94 addr = (void __iomem *)WIN_OFF(i); 54 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
95 55 },
96 writel(0, addr + WIN_BASE_OFF); 56 { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
97 writel(0, addr + WIN_CTRL_OFF); 57 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
98 if (cpu_win_can_remap(i)) { 58 },
99 writel(0, addr + WIN_REMAP_LO_OFF); 59 { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
100 writel(0, addr + WIN_REMAP_HI_OFF); 60 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
101 } 61 },
102 } 62 { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
103 63 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
64 },
104 /* 65 /*
105 * Setup windows for PCIe IO+MEM space. 66 * Window for NAND controller.
106 */ 67 */
107 setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, 68 { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 69 TARGET_DEV_BUS, ATTR_DEV_NAND, -1
109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 70 },
110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
115
116 /* 71 /*
117 * Setup window for NAND controller. 72 * Window for SRAM.
118 */ 73 */
119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 74 { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 75 TARGET_SRAM, ATTR_SRAM, -1
76 },
77 /* End marker */
78 { -1, 0, 0, 0, 0, 0 }
79};
121 80
81void __init kirkwood_setup_cpu_mbus(void)
82{
122 /* 83 /*
123 * Setup window for SRAM. 84 * Disable, clear and configure windows.
124 */ 85 */
125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 86 orion_config_wins(&addr_map_cfg, addr_map_info);
126 TARGET_SRAM, ATTR_SRAM, -1);
127 87
128 /* 88 /*
129 * Setup MBUS dram target info. 89 * Setup MBUS dram target info.
130 */ 90 */
131 kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 91 orion_setup_cpu_mbus_target(&addr_map_cfg, &kirkwood_mbus_dram_info,
132 92 DDR_WINDOW_CPU_BASE);
133 addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
134
135 for (i = 0, cs = 0; i < 4; i++) {
136 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
137 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
138
139 /*
140 * Chip select enabled?
141 */
142 if (size & 1) {
143 struct mbus_dram_window *w;
144
145 w = &kirkwood_mbus_dram_info.cs[cs++];
146 w->cs_index = i;
147 w->mbus_attr = 0xf & ~(1 << i);
148 w->base = base & 0xffff0000;
149 w->size = (size | 0x0000ffff) + 1;
150 }
151 }
152 kirkwood_mbus_dram_info.num_cs = cs;
153} 93}