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authorAndrew Lunn <andrew@lunn.ch>2011-05-15 07:32:48 -0400
committerNicolas Pitre <nico@fluxnic.net>2011-05-16 15:10:50 -0400
commitee9627234dae8d1b8059b2ac39c961ee0932b803 (patch)
tree1a2dfea66908b45439d322729cb6e34a59330682 /arch/arm/mach-kirkwood
parent5e00d3783dd362a34c9816bb582103c9833e4643 (diff)
ARM: orion: Consolidate the XOR platform setup code.
Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Diffstat (limited to 'arch/arm/mach-kirkwood')
-rw-r--r--arch/arm/mach-kirkwood/common.c195
1 files changed, 6 insertions, 189 deletions
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 08847a6f7d10..7c2b5df4aa1c 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
17#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
18#include <linux/dma-mapping.h>
18#include <net/dsa.h> 19#include <net/dsa.h>
19#include <asm/page.h> 20#include <asm/page.h>
20#include <asm/timex.h> 21#include <asm/timex.h>
@@ -27,7 +28,6 @@
27#include <plat/cache-feroceon-l2.h> 28#include <plat/cache-feroceon-l2.h>
28#include <plat/ehci-orion.h> 29#include <plat/ehci-orion.h>
29#include <plat/mvsdio.h> 30#include <plat/mvsdio.h>
30#include <plat/mv_xor.h>
31#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
32#include <plat/common.h> 32#include <plat/common.h>
33#include <plat/time.h> 33#include <plat/time.h>
@@ -364,210 +364,27 @@ void __init kirkwood_crypto_init(void)
364 364
365 365
366/***************************************************************************** 366/*****************************************************************************
367 * XOR
368 ****************************************************************************/
369static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
370 .dram = &kirkwood_mbus_dram_info,
371};
372
373
374/*****************************************************************************
375 * XOR0 367 * XOR0
376 ****************************************************************************/ 368 ****************************************************************************/
377static struct resource kirkwood_xor0_shared_resources[] = {
378 {
379 .name = "xor 0 low",
380 .start = XOR0_PHYS_BASE,
381 .end = XOR0_PHYS_BASE + 0xff,
382 .flags = IORESOURCE_MEM,
383 }, {
384 .name = "xor 0 high",
385 .start = XOR0_HIGH_PHYS_BASE,
386 .end = XOR0_HIGH_PHYS_BASE + 0xff,
387 .flags = IORESOURCE_MEM,
388 },
389};
390
391static struct platform_device kirkwood_xor0_shared = {
392 .name = MV_XOR_SHARED_NAME,
393 .id = 0,
394 .dev = {
395 .platform_data = &kirkwood_xor_shared_data,
396 },
397 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
398 .resource = kirkwood_xor0_shared_resources,
399};
400
401static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
402
403static struct resource kirkwood_xor00_resources[] = {
404 [0] = {
405 .start = IRQ_KIRKWOOD_XOR_00,
406 .end = IRQ_KIRKWOOD_XOR_00,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct mv_xor_platform_data kirkwood_xor00_data = {
412 .shared = &kirkwood_xor0_shared,
413 .hw_id = 0,
414 .pool_size = PAGE_SIZE,
415};
416
417static struct platform_device kirkwood_xor00_channel = {
418 .name = MV_XOR_NAME,
419 .id = 0,
420 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
421 .resource = kirkwood_xor00_resources,
422 .dev = {
423 .dma_mask = &kirkwood_xor_dmamask,
424 .coherent_dma_mask = DMA_BIT_MASK(64),
425 .platform_data = &kirkwood_xor00_data,
426 },
427};
428
429static struct resource kirkwood_xor01_resources[] = {
430 [0] = {
431 .start = IRQ_KIRKWOOD_XOR_01,
432 .end = IRQ_KIRKWOOD_XOR_01,
433 .flags = IORESOURCE_IRQ,
434 },
435};
436
437static struct mv_xor_platform_data kirkwood_xor01_data = {
438 .shared = &kirkwood_xor0_shared,
439 .hw_id = 1,
440 .pool_size = PAGE_SIZE,
441};
442
443static struct platform_device kirkwood_xor01_channel = {
444 .name = MV_XOR_NAME,
445 .id = 1,
446 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
447 .resource = kirkwood_xor01_resources,
448 .dev = {
449 .dma_mask = &kirkwood_xor_dmamask,
450 .coherent_dma_mask = DMA_BIT_MASK(64),
451 .platform_data = &kirkwood_xor01_data,
452 },
453};
454
455static void __init kirkwood_xor0_init(void) 369static void __init kirkwood_xor0_init(void)
456{ 370{
457 kirkwood_clk_ctrl |= CGC_XOR0; 371 kirkwood_clk_ctrl |= CGC_XOR0;
458 platform_device_register(&kirkwood_xor0_shared);
459 372
460 /* 373 orion_xor0_init(&kirkwood_mbus_dram_info,
461 * two engines can't do memset simultaneously, this limitation 374 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
462 * satisfied by removing memset support from one of the engines. 375 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
463 */
464 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
465 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
466 platform_device_register(&kirkwood_xor00_channel);
467
468 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
469 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
470 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
471 platform_device_register(&kirkwood_xor01_channel);
472} 376}
473 377
474 378
475/***************************************************************************** 379/*****************************************************************************
476 * XOR1 380 * XOR1
477 ****************************************************************************/ 381 ****************************************************************************/
478static struct resource kirkwood_xor1_shared_resources[] = {
479 {
480 .name = "xor 1 low",
481 .start = XOR1_PHYS_BASE,
482 .end = XOR1_PHYS_BASE + 0xff,
483 .flags = IORESOURCE_MEM,
484 }, {
485 .name = "xor 1 high",
486 .start = XOR1_HIGH_PHYS_BASE,
487 .end = XOR1_HIGH_PHYS_BASE + 0xff,
488 .flags = IORESOURCE_MEM,
489 },
490};
491
492static struct platform_device kirkwood_xor1_shared = {
493 .name = MV_XOR_SHARED_NAME,
494 .id = 1,
495 .dev = {
496 .platform_data = &kirkwood_xor_shared_data,
497 },
498 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
499 .resource = kirkwood_xor1_shared_resources,
500};
501
502static struct resource kirkwood_xor10_resources[] = {
503 [0] = {
504 .start = IRQ_KIRKWOOD_XOR_10,
505 .end = IRQ_KIRKWOOD_XOR_10,
506 .flags = IORESOURCE_IRQ,
507 },
508};
509
510static struct mv_xor_platform_data kirkwood_xor10_data = {
511 .shared = &kirkwood_xor1_shared,
512 .hw_id = 0,
513 .pool_size = PAGE_SIZE,
514};
515
516static struct platform_device kirkwood_xor10_channel = {
517 .name = MV_XOR_NAME,
518 .id = 2,
519 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
520 .resource = kirkwood_xor10_resources,
521 .dev = {
522 .dma_mask = &kirkwood_xor_dmamask,
523 .coherent_dma_mask = DMA_BIT_MASK(64),
524 .platform_data = &kirkwood_xor10_data,
525 },
526};
527
528static struct resource kirkwood_xor11_resources[] = {
529 [0] = {
530 .start = IRQ_KIRKWOOD_XOR_11,
531 .end = IRQ_KIRKWOOD_XOR_11,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
536static struct mv_xor_platform_data kirkwood_xor11_data = {
537 .shared = &kirkwood_xor1_shared,
538 .hw_id = 1,
539 .pool_size = PAGE_SIZE,
540};
541
542static struct platform_device kirkwood_xor11_channel = {
543 .name = MV_XOR_NAME,
544 .id = 3,
545 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
546 .resource = kirkwood_xor11_resources,
547 .dev = {
548 .dma_mask = &kirkwood_xor_dmamask,
549 .coherent_dma_mask = DMA_BIT_MASK(64),
550 .platform_data = &kirkwood_xor11_data,
551 },
552};
553
554static void __init kirkwood_xor1_init(void) 382static void __init kirkwood_xor1_init(void)
555{ 383{
556 kirkwood_clk_ctrl |= CGC_XOR1; 384 kirkwood_clk_ctrl |= CGC_XOR1;
557 platform_device_register(&kirkwood_xor1_shared);
558 385
559 /* 386 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
560 * two engines can't do memset simultaneously, this limitation 387 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
561 * satisfied by removing memset support from one of the engines.
562 */
563 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
564 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
565 platform_device_register(&kirkwood_xor10_channel);
566
567 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
568 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
569 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
570 platform_device_register(&kirkwood_xor11_channel);
571} 388}
572 389
573 390