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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 13:42:58 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 13:42:58 -0400
commite4862f2f6f5653dfb67f3ba2b6f0bc74516ed51a (patch)
tree1db5a0540a4eecfad9b7daee476b985e82ddc810 /arch/arm/mach-kirkwood
parentec62dbd7eb8e3dddb221da89ecbcea0fc3dee8c1 (diff)
parentb2c1e07b81a126e5846dfc3d36f559d861df59f4 (diff)
Merge branch 'for-2.6.36' into for-2.6.37
Fairly simple conflicts, the most serious ones are the i.MX ones which I suspect now need another rename. Conflicts: arch/arm/mach-mx2/clock_imx27.c arch/arm/mach-mx2/devices.c arch/arm/mach-omap2/board-rx51-peripherals.c arch/arm/mach-omap2/board-zoom2.c sound/soc/fsl/mpc5200_dma.c sound/soc/fsl/mpc5200_dma.h sound/soc/fsl/mpc8610_hpcd.c sound/soc/pxa/spitz.c
Diffstat (limited to 'arch/arm/mach-kirkwood')
-rw-r--r--arch/arm/mach-kirkwood/Kconfig19
-rw-r--r--arch/arm/mach-kirkwood/Makefile2
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c10
-rw-r--r--arch/arm/mach-kirkwood/common.c38
-rw-r--r--arch/arm/mach-kirkwood/common.h5
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c18
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h3
-rw-r--r--arch/arm/mach-kirkwood/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h39
-rw-r--r--arch/arm/mach-kirkwood/include/mach/leds-ns2.h26
-rw-r--r--arch/arm/mach-kirkwood/mpp.c3
-rw-r--r--arch/arm/mach-kirkwood/mpp.h596
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/netspace_v2-setup.c104
-rw-r--r--arch/arm/mach-kirkwood/netxbig_v2-setup.c32
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c29
-rw-r--r--arch/arm/mach-kirkwood/pcie.c174
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c194
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c11
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c39
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.c2
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.h2
24 files changed, 923 insertions, 430 deletions
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3..cc25501b57fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
75 Say 'Y' here if you want your kernel to support the 75 Say 'Y' here if you want your kernel to support the
76 Marvell OpenRD Client Board. 76 Marvell OpenRD Client Board.
77 77
78config MACH_OPENRD_ULTIMATE
79 bool "Marvell OpenRD Ultimate Board"
80 select MACH_OPENRD
81 help
82 Say 'Y' here if you want your kernel to support the
83 Marvell OpenRD Ultimate Board.
84
78config MACH_NETSPACE_V2 85config MACH_NETSPACE_V2
79 bool "LaCie Network Space v2 NAS Board" 86 bool "LaCie Network Space v2 NAS Board"
80 help 87 help
@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
87 Say 'Y' here if you want your kernel to support the 94 Say 'Y' here if you want your kernel to support the
88 LaCie Internet Space v2 NAS. 95 LaCie Internet Space v2 NAS.
89 96
97config MACH_NETSPACE_MAX_V2
98 bool "LaCie Network Space Max v2 NAS Board"
99 help
100 Say 'Y' here if you want your kernel to support the
101 LaCie Network Space Max v2 NAS.
102
90config MACH_NET2BIG_V2 103config MACH_NET2BIG_V2
91 bool "LaCie 2Big Network v2 NAS Board" 104 bool "LaCie 2Big Network v2 NAS Board"
92 help 105 help
@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
99 Say 'Y' here if you want your kernel to support the 112 Say 'Y' here if you want your kernel to support the
100 LaCie 5Big Network v2 NAS. 113 LaCie 5Big Network v2 NAS.
101 114
115config MACH_T5325
116 bool "HP t5325 Thin Client"
117 help
118 Say 'Y' here if you want your kernel to support the
119 HP t5325 Thin Client.
120
102endmenu 121endmenu
103 122
104endif 123endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002..295d7baa6ae1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o 12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o 13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o
14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o 14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o
15obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o
15obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o 16obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o
16obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o 17obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o
18obj-$(CONFIG_MACH_T5325) += t5325-setup.o
17 19
18obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699..8d03bcef5182 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
31#define ATTR_DEV_CS0 0x3e 31#define ATTR_DEV_CS0 0x3e
32#define ATTR_PCIE_IO 0xe0 32#define ATTR_PCIE_IO 0xe0
33#define ATTR_PCIE_MEM 0xe8 33#define ATTR_PCIE_MEM 0xe8
34#define ATTR_PCIE1_IO 0xd0
35#define ATTR_PCIE1_MEM 0xd8
34#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
35 37
36/* 38/*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
106 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
107 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); 110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
109 115
110 /* 116 /*
111 * Setup window for NAND controller. 117 * Setup window for NAND controller.
112 */ 118 */
113 setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
114 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
115 121
116 /* 122 /*
117 * Setup window for SRAM. 123 * Setup window for SRAM.
118 */ 124 */
119 setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_SRAM, ATTR_SRAM, -1); 126 TARGET_SRAM, ATTR_SRAM, -1);
121 127
122 /* 128 /*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 07690132cdbf..0f6ee32678ef 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -45,6 +45,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
45 .length = KIRKWOOD_PCIE_IO_SIZE, 45 .length = KIRKWOOD_PCIE_IO_SIZE,
46 .type = MT_DEVICE, 46 .type = MT_DEVICE,
47 }, { 47 }, {
48 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
49 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
50 .length = KIRKWOOD_PCIE1_IO_SIZE,
51 .type = MT_DEVICE,
52 }, {
48 .virtual = KIRKWOOD_REGS_VIRT_BASE, 53 .virtual = KIRKWOOD_REGS_VIRT_BASE,
49 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), 54 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
50 .length = KIRKWOOD_REGS_SIZE, 55 .length = KIRKWOOD_REGS_SIZE,
@@ -403,7 +408,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
403 u32 dev, rev; 408 u32 dev, rev;
404 409
405 kirkwood_pcie_id(&dev, &rev); 410 kirkwood_pcie_id(&dev, &rev);
406 if (rev == 0) /* catch all Kirkwood Z0's */ 411 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
407 mvsdio_data->clock = 100000000; 412 mvsdio_data->clock = 100000000;
408 else 413 else
409 mvsdio_data->clock = 200000000; 414 mvsdio_data->clock = 200000000;
@@ -848,8 +853,10 @@ int __init kirkwood_find_tclk(void)
848 u32 dev, rev; 853 u32 dev, rev;
849 854
850 kirkwood_pcie_id(&dev, &rev); 855 kirkwood_pcie_id(&dev, &rev);
851 if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || 856
852 rev == MV88F6281_REV_A1)) 857 if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
858 rev == MV88F6281_REV_A1)) ||
859 (dev == MV88F6282_DEV_ID))
853 return 200000000; 860 return 200000000;
854 861
855 return 166666667; 862 return 166666667;
@@ -934,13 +941,22 @@ static char * __init kirkwood_id(void)
934 return "MV88F6192-Z0"; 941 return "MV88F6192-Z0";
935 else if (rev == MV88F6192_REV_A0) 942 else if (rev == MV88F6192_REV_A0)
936 return "MV88F6192-A0"; 943 return "MV88F6192-A0";
944 else if (rev == MV88F6192_REV_A1)
945 return "MV88F6192-A1";
937 else 946 else
938 return "MV88F6192-Rev-Unsupported"; 947 return "MV88F6192-Rev-Unsupported";
939 } else if (dev == MV88F6180_DEV_ID) { 948 } else if (dev == MV88F6180_DEV_ID) {
940 if (rev == MV88F6180_REV_A0) 949 if (rev == MV88F6180_REV_A0)
941 return "MV88F6180-Rev-A0"; 950 return "MV88F6180-Rev-A0";
951 else if (rev == MV88F6180_REV_A1)
952 return "MV88F6180-Rev-A1";
942 else 953 else
943 return "MV88F6180-Rev-Unsupported"; 954 return "MV88F6180-Rev-Unsupported";
955 } else if (dev == MV88F6282_DEV_ID) {
956 if (rev == MV88F6282_REV_A0)
957 return "MV88F6282-Rev-A0";
958 else
959 return "MV88F6282-Rev-Unsupported";
944 } else { 960 } else {
945 return "Device-Unknown"; 961 return "Device-Unknown";
946 } 962 }
@@ -993,12 +1009,14 @@ void __init kirkwood_init(void)
993static int __init kirkwood_clock_gate(void) 1009static int __init kirkwood_clock_gate(void)
994{ 1010{
995 unsigned int curr = readl(CLOCK_GATING_CTRL); 1011 unsigned int curr = readl(CLOCK_GATING_CTRL);
1012 u32 dev, rev;
996 1013
1014 kirkwood_pcie_id(&dev, &rev);
997 printk(KERN_DEBUG "Gating clock of unused units\n"); 1015 printk(KERN_DEBUG "Gating clock of unused units\n");
998 printk(KERN_DEBUG "before: 0x%08x\n", curr); 1016 printk(KERN_DEBUG "before: 0x%08x\n", curr);
999 1017
1000 /* Make sure those units are accessible */ 1018 /* Make sure those units are accessible */
1001 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); 1019 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
1002 1020
1003 /* For SATA: first shutdown the phy */ 1021 /* For SATA: first shutdown the phy */
1004 if (!(kirkwood_clk_ctrl & CGC_SATA0)) { 1022 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -1023,6 +1041,18 @@ static int __init kirkwood_clock_gate(void)
1023 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); 1041 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
1024 } 1042 }
1025 1043
1044 /* For PCIe 1: first shutdown the phy */
1045 if (dev == MV88F6282_DEV_ID) {
1046 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
1047 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
1048 while (1)
1049 if (readl(PCIE1_STATUS) & 0x1)
1050 break;
1051 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
1052 }
1053 } else /* keep this bit set for devices that don't have PCIe1 */
1054 kirkwood_clk_ctrl |= CGC_PEX1;
1055
1026 /* Now gate clock the required units */ 1056 /* Now gate clock the required units */
1027 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); 1057 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
1028 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); 1058 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index c9ab1cb3b39f..95bb0a73adfb 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -19,6 +19,9 @@ struct mtd_partition;
19struct mtd_info; 19struct mtd_info;
20struct kirkwood_asoc_platform_data; 20struct kirkwood_asoc_platform_data;
21 21
22#define KW_PCIE0 (1 << 0)
23#define KW_PCIE1 (1 << 1)
24
22/* 25/*
23 * Basic Kirkwood init functions used early by machine-setup. 26 * Basic Kirkwood init functions used early by machine-setup.
24 */ 27 */
@@ -35,7 +38,7 @@ void kirkwood_ehci_init(void);
35void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); 38void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
36void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); 39void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
37void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); 40void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
38void kirkwood_pcie_init(void); 41void kirkwood_pcie_init(unsigned int portmask);
39void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); 42void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
40void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); 43void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
41void kirkwood_spi_init(void); 44void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4bcace9..16f6691e7c68 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
51}; 51};
52 52
53static unsigned int db88f6281_mpp_config[] __initdata = { 53static unsigned int db88f6281_mpp_config[] __initdata = {
54 MPP0_NF_IO2,
55 MPP1_NF_IO3,
56 MPP2_NF_IO4,
57 MPP3_NF_IO5,
58 MPP4_NF_IO6,
59 MPP5_NF_IO7,
60 MPP18_NF_IO0,
61 MPP19_NF_IO1,
54 MPP37_GPIO, 62 MPP37_GPIO,
55 MPP38_GPIO, 63 MPP38_GPIO,
56 0 64 0
@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
74 82
75static int __init db88f6281_pci_init(void) 83static int __init db88f6281_pci_init(void)
76{ 84{
77 if (machine_is_db88f6281_bp()) 85 if (machine_is_db88f6281_bp()) {
78 kirkwood_pcie_init(); 86 u32 dev, rev;
79 87
88 kirkwood_pcie_id(&dev, &rev);
89 if (dev == MV88F6282_DEV_ID)
90 kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
91 else
92 kirkwood_pcie_init(KW_PCIE0);
93 }
80 return 0; 94 return 0;
81} 95}
82subsys_initcall(db88f6281_pci_init); 96subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f5017c50e..aff0e1327e38 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
59#define CGC_SATA1 (1 << 15) 59#define CGC_SATA1 (1 << 15)
60#define CGC_XOR1 (1 << 16) 60#define CGC_XOR1 (1 << 16)
61#define CGC_CRYPTO (1 << 17) 61#define CGC_CRYPTO (1 << 17)
62#define CGC_PEX1 (1 << 18)
62#define CGC_GE1 (1 << 19) 63#define CGC_GE1 (1 << 19)
63#define CGC_TDM (1 << 20) 64#define CGC_TDM (1 << 20)
64#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) 65#define CGC_RESERVED (0x6 << 21)
65 66
66#endif 67#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a45a67e..9da2eb59180b 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
23#define IRQ_KIRKWOOD_XOR_10 7 23#define IRQ_KIRKWOOD_XOR_10 7
24#define IRQ_KIRKWOOD_XOR_11 8 24#define IRQ_KIRKWOOD_XOR_11 8
25#define IRQ_KIRKWOOD_PCIE 9 25#define IRQ_KIRKWOOD_PCIE 9
26#define IRQ_KIRKWOOD_PCIE1 10
26#define IRQ_KIRKWOOD_GE00_SUM 11 27#define IRQ_KIRKWOOD_GE00_SUM 11
27#define IRQ_KIRKWOOD_GE01_SUM 15 28#define IRQ_KIRKWOOD_GE01_SUM 15
28#define IRQ_KIRKWOOD_USB 19 29#define IRQ_KIRKWOOD_USB 19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 838151d0744b..93fc2ec95e76 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
16 * Marvell Kirkwood address maps. 16 * Marvell Kirkwood address maps.
17 * 17 *
18 * phys 18 * phys
19 * e0000000 PCIe Memory space 19 * e0000000 PCIe #0 Memory space
20 * e8000000 PCIe #1 Memory space
20 * f1000000 on-chip peripheral registers 21 * f1000000 on-chip peripheral registers
21 * f2000000 PCIe I/O space 22 * f2000000 PCIe #0 I/O space
22 * f3000000 NAND controller address window 23 * f3000000 PCIe #1 I/O space
23 * f4000000 Security Accelerator SRAM 24 * f4000000 NAND controller address window
25 * f5000000 Security Accelerator SRAM
24 * 26 *
25 * virt phys size 27 * virt phys size
26 * fee00000 f1000000 1M on-chip peripheral registers 28 * fed00000 f1000000 1M on-chip peripheral registers
27 * fef00000 f2000000 1M PCIe I/O space 29 * fee00000 f2000000 1M PCIe #0 I/O space
30 * fef00000 f3000000 1M PCIe #1 I/O space
28 */ 31 */
29 32
30#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 33#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
31#define KIRKWOOD_SRAM_SIZE SZ_2K 34#define KIRKWOOD_SRAM_SIZE SZ_2K
32 35
33#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 36#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
34#define KIRKWOOD_NAND_MEM_SIZE SZ_1K 37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
35 38
39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
40#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
41#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
42#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
43
36#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 44#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
37#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 45#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
38#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 46#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
39#define KIRKWOOD_PCIE_IO_SIZE SZ_1M 47#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
40 48
41#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 49#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
42#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 50#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
43#define KIRKWOOD_REGS_SIZE SZ_1M 51#define KIRKWOOD_REGS_SIZE SZ_1M
44 52
45#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 53#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
46#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 54#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
47#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M 55#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
48 56
57#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
58#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
59#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
60
49/* 61/*
50 * Register Map 62 * Register Map
51 */ 63 */
@@ -72,6 +84,9 @@
72#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) 84#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
73#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) 85#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
74#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) 86#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
87#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
88#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
89#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
75 90
76#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) 91#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
77 92
@@ -110,8 +125,12 @@
110#define MV88F6192_DEV_ID 0x6192 125#define MV88F6192_DEV_ID 0x6192
111#define MV88F6192_REV_Z0 0 126#define MV88F6192_REV_Z0 0
112#define MV88F6192_REV_A0 2 127#define MV88F6192_REV_A0 2
128#define MV88F6192_REV_A1 3
113 129
114#define MV88F6180_DEV_ID 0x6180 130#define MV88F6180_DEV_ID 0x6180
115#define MV88F6180_REV_A0 2 131#define MV88F6180_REV_A0 2
132#define MV88F6180_REV_A1 3
116 133
134#define MV88F6282_DEV_ID 0x6282
135#define MV88F6282_REV_A0 0
117#endif 136#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
new file mode 100644
index 000000000000..e21272e5f668
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
3 *
4 * Platform data structure for Network Space v2 LED driver
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __MACH_LEDS_NS2_H
12#define __MACH_LEDS_NS2_H
13
14struct ns2_led {
15 const char *name;
16 const char *default_trigger;
17 unsigned cmd;
18 unsigned slow;
19};
20
21struct ns2_led_platform_data {
22 int num_leds;
23 struct ns2_led *leds;
24};
25
26#endif /* __MACH_LEDS_NS2_H */
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f64e38c..065187d177c6 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
23 23
24 kirkwood_pcie_id(&dev, &rev); 24 kirkwood_pcie_id(&dev, &rev);
25 25
26 if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) 26 if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
27 (dev == MV88F6282_DEV_ID))
27 return MPP_F6281_MASK; 28 return MPP_F6281_MASK;
28 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) 29 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
29 return MPP_F6192_MASK; 30 return MPP_F6192_MASK;
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278ed311..9b0a94d85c3e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
11#ifndef __KIRKWOOD_MPP_H 11#ifndef __KIRKWOOD_MPP_H
12#define __KIRKWOOD_MPP_H 12#define __KIRKWOOD_MPP_H
13 13
14#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ 14#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
15 /* MPP number */ ((_num) & 0xff) | \ 15 /* MPP number */ ((_num) & 0xff) | \
16 /* MPP select value */ (((_sel) & 0xf) << 8) | \ 16 /* MPP select value */ (((_sel) & 0xf) << 8) | \
17 /* may be input signal */ ((!!(_in)) << 12) | \ 17 /* may be input signal */ ((!!(_in)) << 12) | \
@@ -19,282 +19,332 @@
19 /* available on F6180 */ ((!!(_F6180)) << 14) | \ 19 /* available on F6180 */ ((!!(_F6180)) << 14) | \
20 /* available on F6190 */ ((!!(_F6190)) << 15) | \ 20 /* available on F6190 */ ((!!(_F6190)) << 15) | \
21 /* available on F6192 */ ((!!(_F6192)) << 16) | \ 21 /* available on F6192 */ ((!!(_F6192)) << 16) | \
22 /* available on F6281 */ ((!!(_F6281)) << 17)) 22 /* available on F6281 */ ((!!(_F6281)) << 17) | \
23 /* available on F6282 */ ((!!(_F6282)) << 18))
23 24
24#define MPP_NUM(x) ((x) & 0xff) 25#define MPP_NUM(x) ((x) & 0xff)
25#define MPP_SEL(x) (((x) >> 8) & 0xf) 26#define MPP_SEL(x) (((x) >> 8) & 0xf)
26 27
27 /* num sel i o 6180 6190 6192 6281 */ 28 /* num sel i o 6180 6190 6192 6281 6282 */
28 29
29#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) 30#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
30#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) 31#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
31 32
32#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) 33#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
33#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) 34#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
34#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) 35#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
35#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) 36#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 )
36 37#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
37#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) 38
38#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) 39#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
39#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) 40#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 )
40 41#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 )
41#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) 42
42#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) 43#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
43#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) 44#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 )
44 45#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 )
45#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) 46
46#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) 47#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
47#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) 48#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 )
48 49#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 )
49#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) 50
50#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) 51#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
51#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) 52#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 )
52 53#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 )
53#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) 54
54#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) 55#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
55#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) 56#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 )
56#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) 57#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 )
57#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) 58#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 )
58 59#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
59#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) 60#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 )
60#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) 61
61#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) 62#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
62#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) 63#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 )
63#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) 64#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 )
64 65#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 )
65#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) 66#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 )
66#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) 67#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
67#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) 68
68 69#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 )
69#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) 70#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 )
70#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) 71#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 )
71#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) 72
72#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) 73#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
73 74#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 )
74#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) 75#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 )
75#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) 76#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 )
76#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) 77#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 )
77#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) 78
78#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) 79#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
79#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) 80#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 )
80#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) 81#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 )
81#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) 82#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 )
82 83#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 )
83#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) 84#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 )
84#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) 85#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 )
85#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) 86#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 )
86#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) 87
87#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) 88#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
88#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) 89#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 )
89#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) 90#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 )
90 91#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 )
91#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) 92#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 )
92#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) 93#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 )
93#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) 94#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 )
94#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) 95
95#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) 96#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
96 97#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 )
97#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) 98#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 )
98#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) 99#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 )
99#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) 100#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 )
100#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) 101
101#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) 102#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
102#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) 103#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 )
103#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) 104#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 )
104 105#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 )
105#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) 106#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 )
106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) 107#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 )
107 108#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
108#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) 109
109#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) 110#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
110#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) 111#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
111 112#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
112#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) 113#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
113#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) 114#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 )
114#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) 115
115#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) 116#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
116#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) 117#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 )
117 118#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 )
118#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) 119#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 )
119#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) 120#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 )
120#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) 121
121#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) 122#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
122#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) 123#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 )
123 124#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 )
124#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) 125#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 )
125#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) 126#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 )
126#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) 127#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 )
127#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) 128#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 )
128#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) 129
129#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) 130#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
130 131#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 )
131#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) 132#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 )
132#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) 133#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 )
133#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) 134#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 )
134 135#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 )
135#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) 136
136#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) 137#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
137 138#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 )
138#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) 139#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 )
139#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) 140#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 )
140 141#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 )
141#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) 142#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 )
142#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) 143#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 )
143#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) 144
144#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) 145#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
145#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) 146#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 )
146#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) 147#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 )
147 148#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 )
148#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) 149#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 )
149#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) 150
150#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) 151#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
151#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) 152#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 )
152#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) 153#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 )
153#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) 154
154 155#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
155#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) 156#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 )
156#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) 157
157#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) 158#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
158#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) 159#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 )
159#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) 160#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 )
160#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) 161#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
161 162#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 )
162#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) 163#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 )
163#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) 164#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
164#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) 165
165#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) 166#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
166#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) 167#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 )
167#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) 168#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 )
168 169#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
169#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) 170#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 )
170#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) 171#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 )
171#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) 172#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
172#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) 173
173#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) 174#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
174 175#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 )
175#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) 176#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 )
176#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) 177#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
177#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) 178#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 )
178#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) 179#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 )
179#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) 180#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
180 181
181#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) 182#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
182#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) 183#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 )
183#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) 184#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 )
184#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) 185#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
185#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) 186#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 )
186 187#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 )
187#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) 188#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
188#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) 189
189#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) 190#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
190#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) 191#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 )
191#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) 192#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 )
192 193#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
193#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) 194#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 )
194#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) 195#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
195#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) 196
196#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) 197#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
197#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) 198#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 )
198 199#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 )
199#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) 200#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
200#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) 201#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 )
201#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) 202#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
202#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) 203
203 204#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
204#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) 205#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 )
205#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) 206#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 )
206#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) 207#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
207#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) 208#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 )
208 209#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
209#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) 210
210#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) 211#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
211#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) 212#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 )
212#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) 213#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 )
213 214#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
214#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) 215#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 )
215#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) 216#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
216#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) 217
217#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) 218#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
218 219#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 )
219#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) 220#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
220#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) 221#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
221#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) 222#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 )
222 223#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
223#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) 224
224#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) 225#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
225#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) 226#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 )
226 227#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
227#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) 228#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
228#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) 229#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
229#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) 230
230#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) 231#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
231#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) 232#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 )
232 233#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 )
233#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) 234#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
234#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) 235#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
235#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) 236
236#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) 237#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
237 238#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 )
238#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) 239#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 )
239#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) 240#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
240#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) 241#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
241#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) 242
242 243#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
243#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) 244#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 )
244#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) 245#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 )
245#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) 246#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
246#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) 247#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
247 248
248#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) 249#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
249#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) 250#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 )
250#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) 251#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
251#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) 252#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
252 253
253#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) 254#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
254#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) 255#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 )
255#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) 256#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
256#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) 257#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 )
257 258#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
258#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) 259
259#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) 260#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
260#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) 261#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 )
261#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) 262#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
262 263#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 )
263#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) 264#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
264#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) 265#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 )
265#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) 266
266#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) 267#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
267 268#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 )
268#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) 269#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 )
269#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) 270#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 )
270#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) 271#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 )
271#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) 272
272 273#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
273#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) 274#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 )
274#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) 275#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 )
275#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) 276#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 )
276#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) 277#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 )
277 278
278#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) 279#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
279#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) 280#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 )
280#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) 281#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 )
281 282#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 )
282#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) 283#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
283#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) 284
284#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) 285#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
285 286#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 )
286#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) 287#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 )
287#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) 288#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 )
288#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) 289#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
289 290
290#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) 291#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
291#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) 292#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 )
292#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) 293#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 )
293 294#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 )
294#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) 295#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
295#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) 296
296#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) 297#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
297#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) 298#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 )
299#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 )
300#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 )
301#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
302
303#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
304#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 )
305#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 )
306#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 )
307#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
308
309#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
310#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 )
311#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
312#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 )
313#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
314
315#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
316#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 )
317#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
318#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 )
319#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
320
321#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
322#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 )
323#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 )
324#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
325
326#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
327#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 )
328#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 )
329#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
330
331#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
332#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 )
333#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 )
334#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
335
336#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
337#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 )
338#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 )
339#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
340
341#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
342#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
343#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 )
344#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 )
345#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 )
346#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 )
347#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
298 348
299#define MPP_MAX 49 349#define MPP_MAX 49
300 350
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711b1c67..c6b92b42eb4e 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
155static int __init mv88f6281gtw_ge_pci_init(void) 155static int __init mv88f6281gtw_ge_pci_init(void)
156{ 156{
157 if (machine_is_mv88f6281gtw_ge()) 157 if (machine_is_mv88f6281gtw_ge())
158 kirkwood_pcie_init(); 158 kirkwood_pcie_init(KW_PCIE0);
159 159
160 return 0; 160 return 0;
161} 161}
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d72681..d26bf324738b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -39,6 +39,7 @@
39#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 40#include <asm/mach/time.h>
41#include <mach/kirkwood.h> 41#include <mach/kirkwood.h>
42#include <mach/leds-ns2.h>
42#include <plat/time.h> 43#include <plat/time.h>
43#include "common.h" 44#include "common.h"
44#include "mpp.h" 45#include "mpp.h"
@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
126 } 127 }
127 if (err) 128 if (err)
128 pr_err("netspace_v2: failed to setup SATA0 power\n"); 129 pr_err("netspace_v2: failed to setup SATA0 power\n");
130
131 if (machine_is_netspace_max_v2()) {
132 err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
133 if (err == 0) {
134 err = gpio_direction_output(
135 NETSPACE_V2_GPIO_SATA1_POWER, 1);
136 if (err)
137 gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
138 }
139 if (err)
140 pr_err("netspace_v2: failed to setup SATA1 power\n");
141 }
129} 142}
130 143
131/***************************************************************************** 144/*****************************************************************************
@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
160 * GPIO LEDs 173 * GPIO LEDs
161 ****************************************************************************/ 174 ****************************************************************************/
162 175
163/*
164 * The blue front LED is wired to a CPLD and can blink in relation with the
165 * SATA activity.
166 *
167 * The following array detail the different LED registers and the combination
168 * of their possible values:
169 *
170 * cmd_led | slow_led | /SATA active | LED state
171 * | | |
172 * 1 | 0 | x | off
173 * - | 1 | x | on
174 * 0 | 0 | 1 | on
175 * 0 | 0 | 0 | blink (rate 300ms)
176 */
177
178#define NETSPACE_V2_GPIO_RED_LED 12 176#define NETSPACE_V2_GPIO_RED_LED 12
179#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
180#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
181
182 177
183static struct gpio_led netspace_v2_gpio_led_pins[] = { 178static struct gpio_led netspace_v2_gpio_led_pins[] = {
184 { 179 {
185 .name = "ns_v2:blue:sata", 180 .name = "ns_v2:red:fail",
186 .default_trigger = "default-on", 181 .gpio = NETSPACE_V2_GPIO_RED_LED,
187 .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD,
188 .active_low = 1,
189 },
190 {
191 .name = "ns_v2:red:fail",
192 .gpio = NETSPACE_V2_GPIO_RED_LED,
193 }, 182 },
194}; 183};
195 184
@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
206 }, 195 },
207}; 196};
208 197
209static void __init netspace_v2_gpio_leds_init(void) 198/*****************************************************************************
210{ 199 * Dual-GPIO CPLD LEDs
211 int err; 200 ****************************************************************************/
212 201
213 /* Configure register slow_led to allow SATA activity LED blinking */ 202#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
214 err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); 203#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
215 if (err == 0) {
216 err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
217 if (err)
218 gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
219 }
220 if (err)
221 pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
222 204
223 platform_device_register(&netspace_v2_gpio_leds); 205static struct ns2_led netspace_v2_led_pins[] = {
224} 206 {
207 .name = "ns_v2:blue:sata",
208 .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD,
209 .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
210 },
211};
212
213static struct ns2_led_platform_data netspace_v2_leds_data = {
214 .num_leds = ARRAY_SIZE(netspace_v2_led_pins),
215 .leds = netspace_v2_led_pins,
216};
217
218static struct platform_device netspace_v2_leds = {
219 .name = "leds-ns2",
220 .id = -1,
221 .dev = {
222 .platform_data = &netspace_v2_leds_data,
223 },
224};
225 225
226/***************************************************************************** 226/*****************************************************************************
227 * Timer 227 * Timer
@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
249 MPP4_NF_IO6, 249 MPP4_NF_IO6,
250 MPP5_NF_IO7, 250 MPP5_NF_IO7,
251 MPP6_SYSRST_OUTn, 251 MPP6_SYSRST_OUTn,
252 MPP8_TW_SDA, 252 MPP7_GPO, /* Fan speed (bit 1) */
253 MPP9_TW_SCK, 253 MPP8_TW0_SDA,
254 MPP9_TW0_SCK,
254 MPP10_UART0_TXD, 255 MPP10_UART0_TXD,
255 MPP11_UART0_RXD, 256 MPP11_UART0_RXD,
256 MPP12_GPO, /* Red led */ 257 MPP12_GPO, /* Red led */
257 MPP14_GPIO, /* USB fuse */ 258 MPP14_GPIO, /* USB fuse */
258 MPP16_GPIO, /* SATA 0 power */ 259 MPP16_GPIO, /* SATA 0 power */
260 MPP17_GPIO, /* SATA 1 power */
259 MPP18_NF_IO0, 261 MPP18_NF_IO0,
260 MPP19_NF_IO1, 262 MPP19_NF_IO1,
261 MPP20_SATA1_ACTn, 263 MPP20_SATA1_ACTn,
262 MPP21_SATA0_ACTn, 264 MPP21_SATA0_ACTn,
265 MPP22_GPIO, /* Fan speed (bit 0) */
266 MPP23_GPIO, /* Fan power */
263 MPP24_GPIO, /* USB mode select */ 267 MPP24_GPIO, /* USB mode select */
264 MPP25_GPIO, /* Fan rotation fail */ 268 MPP25_GPIO, /* Fan rotation fail */
265 MPP26_GPIO, /* USB device vbus */ 269 MPP26_GPIO, /* USB device vbus */
@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
268 MPP30_GPIO, /* Blue led (command register) */ 272 MPP30_GPIO, /* Blue led (command register) */
269 MPP31_GPIO, /* Board power off */ 273 MPP31_GPIO, /* Board power off */
270 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ 274 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
275 MPP33_GPO, /* Fan speed (bit 2) */
271 0 276 0
272}; 277};
273 278
@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
299 i2c_register_board_info(0, netspace_v2_i2c_info, 304 i2c_register_board_info(0, netspace_v2_i2c_info,
300 ARRAY_SIZE(netspace_v2_i2c_info)); 305 ARRAY_SIZE(netspace_v2_i2c_info));
301 306
302 netspace_v2_gpio_leds_init(); 307 platform_device_register(&netspace_v2_leds);
308 platform_device_register(&netspace_v2_gpio_leds);
303 platform_device_register(&netspace_v2_gpio_buttons); 309 platform_device_register(&netspace_v2_gpio_buttons);
304 310
305 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && 311 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
332 .timer = &netspace_v2_timer, 338 .timer = &netspace_v2_timer,
333MACHINE_END 339MACHINE_END
334#endif 340#endif
341
342#ifdef CONFIG_MACH_NETSPACE_MAX_V2
343MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
344 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
345 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
346 .boot_params = 0x00000100,
347 .init_machine = netspace_v2_init,
348 .map_io = kirkwood_map_io,
349 .init_irq = kirkwood_init_irq,
350 .timer = &netspace_v2_timer,
351MACHINE_END
352#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb0228e4f..2bd14c5079de 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
270 MPP3_SPI_MISO, 270 MPP3_SPI_MISO,
271 MPP6_SYSRST_OUTn, 271 MPP6_SYSRST_OUTn,
272 MPP7_GPO, /* Request power-off */ 272 MPP7_GPO, /* Request power-off */
273 MPP8_TW_SDA, 273 MPP8_TW0_SDA,
274 MPP9_TW_SCK, 274 MPP9_TW0_SCK,
275 MPP10_UART0_TXD, 275 MPP10_UART0_TXD,
276 MPP11_UART0_RXD, 276 MPP11_UART0_RXD,
277 MPP13_GPIO, /* Rear power switch (on|auto) */ 277 MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
306 MPP3_SPI_MISO, 306 MPP3_SPI_MISO,
307 MPP6_SYSRST_OUTn, 307 MPP6_SYSRST_OUTn,
308 MPP7_GPO, /* Request power-off */ 308 MPP7_GPO, /* Request power-off */
309 MPP8_TW_SDA, 309 MPP8_TW0_SDA,
310 MPP9_TW_SCK, 310 MPP9_TW0_SCK,
311 MPP10_UART0_TXD, 311 MPP10_UART0_TXD,
312 MPP11_UART0_RXD, 312 MPP11_UART0_RXD,
313 MPP13_GPIO, /* Rear power switch (on|auto) */ 313 MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
315 MPP15_GPIO, /* Rear power switch (auto|off) */ 315 MPP15_GPIO, /* Rear power switch (auto|off) */
316 MPP16_GPIO, /* SATA HDD1 power */ 316 MPP16_GPIO, /* SATA HDD1 power */
317 MPP17_GPIO, /* SATA HDD2 power */ 317 MPP17_GPIO, /* SATA HDD2 power */
318 MPP20_GE1_0, 318 MPP20_GE1_TXD0,
319 MPP21_GE1_1, 319 MPP21_GE1_TXD1,
320 MPP22_GE1_2, 320 MPP22_GE1_TXD2,
321 MPP23_GE1_3, 321 MPP23_GE1_TXD3,
322 MPP24_GE1_4, 322 MPP24_GE1_RXD0,
323 MPP25_GE1_5, 323 MPP25_GE1_RXD1,
324 MPP26_GE1_6, 324 MPP26_GE1_RXD2,
325 MPP27_GE1_7, 325 MPP27_GE1_RXD3,
326 MPP28_GPIO, /* USB enable host vbus */ 326 MPP28_GPIO, /* USB enable host vbus */
327 MPP29_GPIO, /* CPLD extension ALE */ 327 MPP29_GPIO, /* CPLD extension ALE */
328 MPP30_GE1_10, 328 MPP30_GE1_RXCTL,
329 MPP31_GE1_11, 329 MPP31_GE1_RXCLK,
330 MPP32_GE1_12, 330 MPP32_GE1_TCLKOUT,
331 MPP33_GE1_13, 331 MPP33_GE1_TXCTL,
332 MPP34_GPIO, /* Rear Push button */ 332 MPP34_GPIO, /* Rear Push button */
333 MPP35_GPIO, /* Inhibit switch power-off */ 333 MPP35_GPIO, /* Inhibit switch power-off */
334 MPP36_GPIO, /* SATA HDD1 presence */ 334 MPP36_GPIO, /* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index e36067ad3aca..fd06be618815 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-kirkwood/openrd-setup.c 2 * arch/arm/mach-kirkwood/openrd-setup.c
3 * 3 *
4 * Marvell OpenRD (Base|Client) Board Setup 4 * Marvell OpenRD (Base|Client|Ultimate) Board Setup
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
@@ -80,9 +80,15 @@ static void __init openrd_init(void)
80 80
81 kirkwood_ehci_init(); 81 kirkwood_ehci_init();
82 82
83 if (machine_is_openrd_ultimate()) {
84 openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
85 openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
86 }
87
83 kirkwood_ge00_init(&openrd_ge00_data); 88 kirkwood_ge00_init(&openrd_ge00_data);
84 if (machine_is_openrd_client()) 89 if (!machine_is_openrd_base())
85 kirkwood_ge01_init(&openrd_ge01_data); 90 kirkwood_ge01_init(&openrd_ge01_data);
91
86 kirkwood_sata_init(&openrd_sata_data); 92 kirkwood_sata_init(&openrd_sata_data);
87 kirkwood_sdio_init(&openrd_mvsdio_data); 93 kirkwood_sdio_init(&openrd_mvsdio_data);
88 94
@@ -97,8 +103,10 @@ static void __init openrd_init(void)
97 103
98static int __init openrd_pci_init(void) 104static int __init openrd_pci_init(void)
99{ 105{
100 if (machine_is_openrd_base() || machine_is_openrd_client()) 106 if (machine_is_openrd_base() ||
101 kirkwood_pcie_init(); 107 machine_is_openrd_client() ||
108 machine_is_openrd_ultimate())
109 kirkwood_pcie_init(KW_PCIE0);
102 110
103 return 0; 111 return 0;
104} 112}
@@ -129,3 +137,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
129 .timer = &kirkwood_timer, 137 .timer = &kirkwood_timer,
130MACHINE_END 138MACHINE_END
131#endif 139#endif
140
141#ifdef CONFIG_MACH_OPENRD_ULTIMATE
142MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
143 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
144 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
145 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
146 .boot_params = 0x00000100,
147 .init_machine = openrd_init,
148 .map_io = kirkwood_map_io,
149 .init_irq = kirkwood_init_irq,
150 .timer = &kirkwood_timer,
151MACHINE_END
152#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff50d39..55e7f00836b7 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
18#include <mach/bridge-regs.h> 18#include <mach/bridge-regs.h>
19#include "common.h" 19#include "common.h"
20 20
21void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
22{
23 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
24 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
25}
21 26
22#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) 27struct pcie_port {
28 u8 root_bus_nr;
29 void __iomem *base;
30 spinlock_t conf_lock;
31 int irq;
32 struct resource res[2];
33};
23 34
24void __init kirkwood_pcie_id(u32 *dev, u32 *rev) 35static int pcie_port_map[2];
36static int num_pcie_ports;
37
38static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
25{ 39{
26 *dev = orion_pcie_dev_id(PCIE_BASE); 40 struct pci_sys_data *sys = bus->sysdata;
27 *rev = orion_pcie_rev(PCIE_BASE); 41 return sys->private_data;
28} 42}
29 43
30static int pcie_valid_config(int bus, int dev) 44static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
31{ 45{
32 /* 46 /*
33 * Don't go out when trying to access -- 47 * Don't go out when trying to access --
34 * 1. nonexisting device on local bus 48 * 1. nonexisting device on local bus
35 * 2. where there's no device connected (no link) 49 * 2. where there's no device connected (no link)
36 */ 50 */
37 if (bus == 0 && dev == 0) 51 if (bus == pp->root_bus_nr && dev == 0)
38 return 1; 52 return 1;
39 53
40 if (!orion_pcie_link_up(PCIE_BASE)) 54 if (!orion_pcie_link_up(pp->base))
41 return 0; 55 return 0;
42 56
43 if (bus == 0 && dev != 1) 57 if (bus == pp->root_bus_nr && dev != 1)
44 return 0; 58 return 0;
45 59
46 return 1; 60 return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
52 * and then reading the PCIE_CONF_DATA register. Need to make sure these 66 * and then reading the PCIE_CONF_DATA register. Need to make sure these
53 * transactions are atomic. 67 * transactions are atomic.
54 */ 68 */
55static DEFINE_SPINLOCK(kirkwood_pcie_lock);
56 69
57static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 70static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
58 int size, u32 *val) 71 int size, u32 *val)
59{ 72{
73 struct pcie_port *pp = bus_to_port(bus);
60 unsigned long flags; 74 unsigned long flags;
61 int ret; 75 int ret;
62 76
63 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 77 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
64 *val = 0xffffffff; 78 *val = 0xffffffff;
65 return PCIBIOS_DEVICE_NOT_FOUND; 79 return PCIBIOS_DEVICE_NOT_FOUND;
66 } 80 }
67 81
68 spin_lock_irqsave(&kirkwood_pcie_lock, flags); 82 spin_lock_irqsave(&pp->conf_lock, flags);
69 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 83 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
70 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); 84 spin_unlock_irqrestore(&pp->conf_lock, flags);
71 85
72 return ret; 86 return ret;
73} 87}
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
75static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 89static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
76 int where, int size, u32 val) 90 int where, int size, u32 val)
77{ 91{
92 struct pcie_port *pp = bus_to_port(bus);
78 unsigned long flags; 93 unsigned long flags;
79 int ret; 94 int ret;
80 95
81 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 96 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
82 return PCIBIOS_DEVICE_NOT_FOUND; 97 return PCIBIOS_DEVICE_NOT_FOUND;
83 98
84 spin_lock_irqsave(&kirkwood_pcie_lock, flags); 99 spin_lock_irqsave(&pp->conf_lock, flags);
85 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 100 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
86 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); 101 spin_unlock_irqrestore(&pp->conf_lock, flags);
87 102
88 return ret; 103 return ret;
89} 104}
@@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = {
93 .write = pcie_wr_conf, 108 .write = pcie_wr_conf,
94}; 109};
95 110
96 111static void __init pcie0_ioresources_init(struct pcie_port *pp)
97static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
98{ 112{
99 struct resource *res; 113 pp->base = (void __iomem *)PCIE_VIRT_BASE;
100 extern unsigned int kirkwood_clk_ctrl; 114 pp->irq = IRQ_KIRKWOOD_PCIE;
101 115
102 /* 116 /*
103 * Generic PCIe unit setup. 117 * IORESOURCE_IO
104 */ 118 */
105 orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); 119 pp->res[0].name = "PCIe 0 I/O Space";
120 pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
121 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
122 pp->res[0].flags = IORESOURCE_IO;
106 123
107 /* 124 /*
108 * Request resources. 125 * IORESOURCE_MEM
109 */ 126 */
110 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 127 pp->res[1].name = "PCIe 0 MEM";
111 if (!res) 128 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
112 panic("pcie_setup unable to alloc resources"); 129 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
130 pp->res[1].flags = IORESOURCE_MEM;
131}
132
133static void __init pcie1_ioresources_init(struct pcie_port *pp)
134{
135 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
136 pp->irq = IRQ_KIRKWOOD_PCIE1;
113 137
114 /* 138 /*
115 * IORESOURCE_IO 139 * IORESOURCE_IO
116 */ 140 */
117 res[0].name = "PCIe I/O Space"; 141 pp->res[0].name = "PCIe 1 I/O Space";
118 res[0].flags = IORESOURCE_IO; 142 pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
119 res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; 143 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
120 res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; 144 pp->res[0].flags = IORESOURCE_IO;
121 if (request_resource(&ioport_resource, &res[0]))
122 panic("Request PCIe IO resource failed\n");
123 sys->resource[0] = &res[0];
124 145
125 /* 146 /*
126 * IORESOURCE_MEM 147 * IORESOURCE_MEM
127 */ 148 */
128 res[1].name = "PCIe Memory Space"; 149 pp->res[1].name = "PCIe 1 MEM";
129 res[1].flags = IORESOURCE_MEM; 150 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
130 res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE; 151 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
131 res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; 152 pp->res[1].flags = IORESOURCE_MEM;
132 if (request_resource(&iomem_resource, &res[1])) 153}
133 panic("Request PCIe Memory resource failed\n"); 154
134 sys->resource[1] = &res[1]; 155static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
156{
157 extern unsigned int kirkwood_clk_ctrl;
158 struct pcie_port *pp;
159 int index;
135 160
161 if (nr >= num_pcie_ports)
162 return 0;
163
164 index = pcie_port_map[nr];
165 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
166
167 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
168 if (!pp)
169 panic("PCIe: failed to allocate pcie_port data");
170 sys->private_data = pp;
171 pp->root_bus_nr = sys->busnr;
172 spin_lock_init(&pp->conf_lock);
173
174 switch (index) {
175 case 0:
176 kirkwood_clk_ctrl |= CGC_PEX0;
177 pcie0_ioresources_init(pp);
178 break;
179 case 1:
180 kirkwood_clk_ctrl |= CGC_PEX1;
181 pcie1_ioresources_init(pp);
182 break;
183 default:
184 panic("PCIe setup: invalid controller %d", index);
185 }
186
187 if (request_resource(&ioport_resource, &pp->res[0]))
188 panic("Request PCIe%d IO resource failed\n", index);
189 if (request_resource(&iomem_resource, &pp->res[1]))
190 panic("Request PCIe%d Memory resource failed\n", index);
191
192 sys->resource[0] = &pp->res[0];
193 sys->resource[1] = &pp->res[1];
136 sys->resource[2] = NULL; 194 sys->resource[2] = NULL;
137 sys->io_offset = 0; 195 sys->io_offset = 0;
138 196
139 kirkwood_clk_ctrl |= CGC_PEX0; 197 /*
198 * Generic PCIe unit setup.
199 */
200 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
201
202 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
140 203
141 return 1; 204 return 1;
142} 205}
@@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
163{ 226{
164 struct pci_bus *bus; 227 struct pci_bus *bus;
165 228
166 if (nr == 0) { 229 if (nr < num_pcie_ports) {
167 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 230 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
168 } else { 231 } else {
169 bus = NULL; 232 bus = NULL;
@@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
175 238
176static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 239static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
177{ 240{
178 return IRQ_KIRKWOOD_PCIE; 241 struct pcie_port *pp = bus_to_port(dev->bus);
242
243 return pp->irq;
179} 244}
180 245
181static struct hw_pci kirkwood_pci __initdata = { 246static struct hw_pci kirkwood_pci __initdata = {
182 .nr_controllers = 1,
183 .swizzle = pci_std_swizzle, 247 .swizzle = pci_std_swizzle,
184 .setup = kirkwood_pcie_setup, 248 .setup = kirkwood_pcie_setup,
185 .scan = kirkwood_pcie_scan_bus, 249 .scan = kirkwood_pcie_scan_bus,
186 .map_irq = kirkwood_pcie_map_irq, 250 .map_irq = kirkwood_pcie_map_irq,
187}; 251};
188 252
189void __init kirkwood_pcie_init(void) 253static void __init add_pcie_port(int index, unsigned long base)
190{ 254{
255 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
256
257 if (orion_pcie_link_up((void __iomem *)base)) {
258 printk(KERN_INFO "link up\n");
259 pcie_port_map[num_pcie_ports++] = index;
260 } else
261 printk(KERN_INFO "link down, ignoring\n");
262}
263
264void __init kirkwood_pcie_init(unsigned int portmask)
265{
266 if (portmask & KW_PCIE0)
267 add_pcie_port(0, PCIE_VIRT_BASE);
268
269 if (portmask & KW_PCIE1)
270 add_pcie_port(1, PCIE1_VIRT_BASE);
271
272 kirkwood_pci.nr_controllers = num_pcie_ports;
191 pci_common_init(&kirkwood_pci); 273 pci_common_init(&kirkwood_pci);
192} 274}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304158f6..c34718c2cfe5 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
71static int __init rd88f6192_pci_init(void) 71static int __init rd88f6192_pci_init(void)
72{ 72{
73 if (machine_is_rd88f6192_nas()) 73 if (machine_is_rd88f6192_nas())
74 kirkwood_pcie_init(); 74 kirkwood_pcie_init(KW_PCIE0);
75 75
76 return 0; 76 return 0;
77} 77}
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708ddbc83e..3d1477135e12 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
107static int __init rd88f6281_pci_init(void) 107static int __init rd88f6281_pci_init(void)
108{ 108{
109 if (machine_is_rd88f6281()) 109 if (machine_is_rd88f6281())
110 kirkwood_pcie_init(); 110 kirkwood_pcie_init(KW_PCIE0);
111 111
112 return 0; 112 return 0;
113} 113}
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
new file mode 100644
index 000000000000..d01bf89cedbe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -0,0 +1,194 @@
1/*
2 *
3 * HP t5325 Thin Client setup
4 *
5 * Copyright (C) 2010 Martin Michlmayr <tbm@cyrius.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/physmap.h>
17#include <linux/spi/flash.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/orion_spi.h>
20#include <linux/i2c.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/ata_platform.h>
23#include <linux/gpio.h>
24#include <linux/gpio_keys.h>
25#include <linux/input.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <mach/kirkwood.h>
29#include "common.h"
30#include "mpp.h"
31
32struct mtd_partition hp_t5325_partitions[] = {
33 {
34 .name = "u-boot env",
35 .size = SZ_64K,
36 .offset = SZ_512K + SZ_256K,
37 },
38 {
39 .name = "permanent u-boot env",
40 .size = SZ_64K,
41 .offset = MTDPART_OFS_APPEND,
42 .mask_flags = MTD_WRITEABLE,
43 },
44 {
45 .name = "HP env",
46 .size = SZ_64K,
47 .offset = MTDPART_OFS_APPEND,
48 },
49 {
50 .name = "u-boot",
51 .size = SZ_512K,
52 .offset = 0,
53 .mask_flags = MTD_WRITEABLE,
54 },
55 {
56 .name = "SSD firmware",
57 .size = SZ_256K,
58 .offset = SZ_512K,
59 },
60};
61
62const struct flash_platform_data hp_t5325_flash = {
63 .type = "mx25l8005",
64 .name = "spi_flash",
65 .parts = hp_t5325_partitions,
66 .nr_parts = ARRAY_SIZE(hp_t5325_partitions),
67};
68
69struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
70 {
71 .modalias = "m25p80",
72 .platform_data = &hp_t5325_flash,
73 .irq = -1,
74 },
75};
76
77static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
78 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
79};
80
81static struct mv_sata_platform_data hp_t5325_sata_data = {
82 .n_ports = 2,
83};
84
85static struct gpio_keys_button hp_t5325_buttons[] = {
86 {
87 .code = KEY_POWER,
88 .gpio = 45,
89 .desc = "Power",
90 .active_low = 1,
91 },
92};
93
94static struct gpio_keys_platform_data hp_t5325_button_data = {
95 .buttons = hp_t5325_buttons,
96 .nbuttons = ARRAY_SIZE(hp_t5325_buttons),
97};
98
99static struct platform_device hp_t5325_button_device = {
100 .name = "gpio-keys",
101 .id = -1,
102 .num_resources = 0,
103 .dev = {
104 .platform_data = &hp_t5325_button_data,
105 }
106};
107
108static unsigned int hp_t5325_mpp_config[] __initdata = {
109 MPP0_NF_IO2,
110 MPP1_SPI_MOSI,
111 MPP2_SPI_SCK,
112 MPP3_SPI_MISO,
113 MPP4_NF_IO6,
114 MPP5_NF_IO7,
115 MPP6_SYSRST_OUTn,
116 MPP7_SPI_SCn,
117 MPP8_TW0_SDA,
118 MPP9_TW0_SCK,
119 MPP10_UART0_TXD,
120 MPP11_UART0_RXD,
121 MPP12_SD_CLK,
122 MPP13_GPIO,
123 MPP14_GPIO,
124 MPP15_GPIO,
125 MPP16_GPIO,
126 MPP17_GPIO,
127 MPP18_NF_IO0,
128 MPP19_NF_IO1,
129 MPP20_GPIO,
130 MPP21_GPIO,
131 MPP22_GPIO,
132 MPP23_GPIO,
133 MPP32_GPIO,
134 MPP33_GE1_TXCTL,
135 MPP39_AU_I2SBCLK,
136 MPP40_AU_I2SDO,
137 MPP41_AU_I2SLRCLK,
138 MPP42_AU_I2SMCLK,
139 MPP45_GPIO, /* Power button */
140 MPP48_GPIO, /* Board power off */
141 0
142};
143
144#define HP_T5325_GPIO_POWER_OFF 48
145
146static void hp_t5325_power_off(void)
147{
148 gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
149}
150
151static void __init hp_t5325_init(void)
152{
153 /*
154 * Basic setup. Needs to be called early.
155 */
156 kirkwood_init();
157 kirkwood_mpp_conf(hp_t5325_mpp_config);
158
159 kirkwood_uart0_init();
160 spi_register_board_info(hp_t5325_spi_slave_info,
161 ARRAY_SIZE(hp_t5325_spi_slave_info));
162 kirkwood_spi_init();
163 kirkwood_i2c_init();
164 kirkwood_ge00_init(&hp_t5325_ge00_data);
165 kirkwood_sata_init(&hp_t5325_sata_data);
166 kirkwood_ehci_init();
167 platform_device_register(&hp_t5325_button_device);
168
169 if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
170 gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
171 pm_power_off = hp_t5325_power_off;
172 else
173 pr_err("t5325: failed to configure power-off GPIO\n");
174}
175
176static int __init hp_t5325_pci_init(void)
177{
178 if (machine_is_t5325())
179 kirkwood_pcie_init(KW_PCIE0);
180
181 return 0;
182}
183subsys_initcall(hp_t5325_pci_init);
184
185MACHINE_START(T5325, "HP t5325 Thin Client")
186 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
187 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
188 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
189 .boot_params = 0x00000100,
190 .init_machine = hp_t5325_init,
191 .map_io = kirkwood_map_io,
192 .init_irq = kirkwood_init_irq,
193 .timer = &kirkwood_timer,
194MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0fe80e0..a5bd7fde04a9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
74 MPP3_SPI_MISO, 74 MPP3_SPI_MISO,
75 MPP4_SATA1_ACTn, 75 MPP4_SATA1_ACTn,
76 MPP5_SATA0_ACTn, 76 MPP5_SATA0_ACTn,
77 MPP8_TW_SDA, 77 MPP8_TW0_SDA,
78 MPP9_TW_SCK, 78 MPP9_TW0_SCK,
79 MPP10_UART0_TXD, 79 MPP10_UART0_TXD,
80 MPP11_UART0_RXD, 80 MPP11_UART0_RXD,
81 MPP13_UART1_TXD, /* PIC controller */ 81 MPP13_UART1_TXD, /* PIC controller */
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
83 MPP15_GPIO, /* USB Copy button */ 83 MPP15_GPIO, /* USB Copy button */
84 MPP16_GPIO, /* Reset button */ 84 MPP16_GPIO, /* Reset button */
85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
86 MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
86 0 87 0
87}; 88};
88 89
@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
110 111
111static int __init ts219_pci_init(void) 112static int __init ts219_pci_init(void)
112{ 113{
113 if (machine_is_ts219()) 114 if (machine_is_ts219())
114 kirkwood_pcie_init(); 115 kirkwood_pcie_init(KW_PCIE0);
115 116
116 return 0; 117 return 0;
117} 118}
118subsys_initcall(ts219_pci_init); 119subsys_initcall(ts219_pci_init);
119 120
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d9e74b..2e14afef07a2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -2,7 +2,7 @@
2 * 2 *
3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup 3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
4 * 4 *
5 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> 5 * Copyright (C) 2009-2010 Martin Michlmayr <tbm@cyrius.com>
6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> 6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
@@ -17,6 +17,7 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/mv643xx_eth.h> 18#include <linux/mv643xx_eth.h>
19#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
20#include <linux/gpio.h>
20#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
21#include <linux/input.h> 22#include <linux/input.h>
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
@@ -26,6 +27,8 @@
26#include "mpp.h" 27#include "mpp.h"
27#include "tsx1x-common.h" 28#include "tsx1x-common.h"
28 29
30#define QNAP_TS41X_JUMPER_JP1 45
31
29static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { 32static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
30 I2C_BOARD_INFO("s35390a", 0x30), 33 I2C_BOARD_INFO("s35390a", 0x30),
31}; 34};
@@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
78 MPP3_SPI_MISO, 81 MPP3_SPI_MISO,
79 MPP6_SYSRST_OUTn, 82 MPP6_SYSRST_OUTn,
80 MPP7_PEX_RST_OUTn, 83 MPP7_PEX_RST_OUTn,
81 MPP8_TW_SDA, 84 MPP8_TW0_SDA,
82 MPP9_TW_SCK, 85 MPP9_TW0_SCK,
83 MPP10_UART0_TXD, 86 MPP10_UART0_TXD,
84 MPP11_UART0_RXD, 87 MPP11_UART0_RXD,
85 MPP13_UART1_TXD, /* PIC controller */ 88 MPP13_UART1_TXD, /* PIC controller */
86 MPP14_UART1_RXD, /* PIC controller */ 89 MPP14_UART1_RXD, /* PIC controller */
87 MPP15_SATA0_ACTn, 90 MPP15_SATA0_ACTn,
88 MPP16_SATA1_ACTn, 91 MPP16_SATA1_ACTn,
89 MPP20_GE1_0, 92 MPP20_GE1_TXD0,
90 MPP21_GE1_1, 93 MPP21_GE1_TXD1,
91 MPP22_GE1_2, 94 MPP22_GE1_TXD2,
92 MPP23_GE1_3, 95 MPP23_GE1_TXD3,
93 MPP24_GE1_4, 96 MPP24_GE1_RXD0,
94 MPP25_GE1_5, 97 MPP25_GE1_RXD1,
95 MPP26_GE1_6, 98 MPP26_GE1_RXD2,
96 MPP27_GE1_7, 99 MPP27_GE1_RXD3,
97 MPP30_GE1_10, 100 MPP30_GE1_RXCTL,
98 MPP31_GE1_11, 101 MPP31_GE1_RXCLK,
99 MPP32_GE1_12, 102 MPP32_GE1_TCLKOUT,
100 MPP33_GE1_13, 103 MPP33_GE1_TXCTL,
101 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 104 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
102 MPP37_GPIO, /* Reset button */ 105 MPP37_GPIO, /* Reset button */
103 MPP43_GPIO, /* USB Copy button */ 106 MPP43_GPIO, /* USB Copy button */
104 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ 107 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */
105 MPP45_GPIO, /* JP1: 0: console, 1: LCD */ 108 MPP45_GPIO, /* JP1: 0: LCD, 1: serial console */
106 MPP46_GPIO, /* External SATA HDD1 error indicator */ 109 MPP46_GPIO, /* External SATA HDD1 error indicator */
107 MPP47_GPIO, /* External SATA HDD2 error indicator */ 110 MPP47_GPIO, /* External SATA HDD2 error indicator */
108 MPP48_GPIO, /* External SATA HDD3 error indicator */ 111 MPP48_GPIO, /* External SATA HDD3 error indicator */
@@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void)
131 134
132 pm_power_off = qnap_tsx1x_power_off; 135 pm_power_off = qnap_tsx1x_power_off;
133 136
137 if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
138 gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
134} 139}
135 140
136static int __init ts41x_pci_init(void) 141static int __init ts41x_pci_init(void)
137{ 142{
138 if (machine_is_ts41x()) 143 if (machine_is_ts41x())
139 kirkwood_pcie_init(); 144 kirkwood_pcie_init(KW_PCIE0);
140 145
141 return 0; 146 return 0;
142} 147}
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
index 7221c20b2afa..f781164e623f 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -77,7 +77,7 @@ struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
77 }, 77 },
78}; 78};
79 79
80void qnap_tsx1x_register_flash(void) 80void __init qnap_tsx1x_register_flash(void)
81{ 81{
82 spi_register_board_info(qnap_tsx1x_spi_slave_info, 82 spi_register_board_info(qnap_tsx1x_spi_slave_info,
83 ARRAY_SIZE(qnap_tsx1x_spi_slave_info)); 83 ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
index 9a592962a6ea..7fa037361b55 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.h
+++ b/arch/arm/mach-kirkwood/tsx1x-common.h
@@ -1,7 +1,7 @@
1#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H 1#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
2#define __ARCH_KIRKWOOD_TSX1X_COMMON_H 2#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
3 3
4extern void qnap_tsx1x_register_flash(void); 4extern void __init qnap_tsx1x_register_flash(void);
5extern void qnap_tsx1x_power_off(void); 5extern void qnap_tsx1x_power_off(void);
6 6
7#endif 7#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 08:35:35 -0500