diff options
author | Thomas Reitmayr <treitmayr@devbase.at> | 2009-06-01 07:38:34 -0400 |
---|---|---|
committer | Nicolas Pitre <nico@cam.org> | 2009-06-08 13:04:59 -0400 |
commit | 054bd3f053de54c81b20df11f354476389826e61 (patch) | |
tree | 9e2a70dac9ee0619e32d95cd96b378e290167ce6 /arch/arm/mach-kirkwood/include | |
parent | 6462c6160af557c310d5941f4700ea2c7f6c67b2 (diff) |
[ARM] Kirkwood: Add the watchdog timer as a platform device.
The Kirkwood architecture uses the same watchdog device as the Orion
architecture. This patch adds orion5x_wdt as a platform device for
Kirkwood.
Signed-off-by: Thomas Reitmayr <treitmayr@devbase.at>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-kirkwood/include')
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 00d96abb718c..9e80d9232c83 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |||
@@ -17,12 +17,15 @@ | |||
17 | #define CPU_RESET 0x00000002 | 17 | #define CPU_RESET 0x00000002 |
18 | 18 | ||
19 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | 19 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) |
20 | #define WDT_RESET_OUT_EN 0x00000002 | ||
20 | #define SOFT_RESET_OUT_EN 0x00000004 | 21 | #define SOFT_RESET_OUT_EN 0x00000004 |
21 | 22 | ||
22 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | 23 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) |
23 | #define SOFT_RESET 0x00000001 | 24 | #define SOFT_RESET 0x00000001 |
24 | 25 | ||
25 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | 26 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) |
27 | #define WDT_INT_REQ 0x0008 | ||
28 | |||
26 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | 29 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) |
27 | #define BRIDGE_INT_TIMER0 0x0002 | 30 | #define BRIDGE_INT_TIMER0 0x0002 |
28 | #define BRIDGE_INT_TIMER1 0x0004 | 31 | #define BRIDGE_INT_TIMER1 0x0004 |