aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-ixp4xx
diff options
context:
space:
mode:
authorKrzysztof Hałasa <khc@pm.waw.pl>2009-11-14 16:55:42 -0500
committerKrzysztof Hałasa <khc@pm.waw.pl>2009-12-05 10:58:39 -0500
commit58e570d1182a9dc3bc52d8dc508c6bd5b2d279c7 (patch)
tree1760943bfb8879565665e8b33e3b9df68f08086b /arch/arm/mach-ixp4xx
parent28f85cd3f65808cde50bb0e395043f38c3efa1cb (diff)
IXP4xx: Drop "__ixp4xx_" prefix from in/out/ioread/iowrite functions for clarity.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Diffstat (limited to 'arch/arm/mach-ixp4xx')
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h150
1 files changed, 55 insertions, 95 deletions
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 061a1f144a01..c06d4a2911a6 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -243,25 +243,8 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
243 * transaction. This means that we need to override the default 243 * transaction. This means that we need to override the default
244 * I/O functions. 244 * I/O functions.
245 */ 245 */
246#define outb(p, v) __ixp4xx_outb(p, v)
247#define outw(p, v) __ixp4xx_outw(p, v)
248#define outl(p, v) __ixp4xx_outl(p, v)
249
250#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
251#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
252#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
253 246
254#define inb(p) __ixp4xx_inb(p) 247static inline void outb(u8 value, u32 addr)
255#define inw(p) __ixp4xx_inw(p)
256#define inl(p) __ixp4xx_inl(p)
257
258#define insb(p, v, l) __ixp4xx_insb(p, v, l)
259#define insw(p, v, l) __ixp4xx_insw(p, v, l)
260#define insl(p, v, l) __ixp4xx_insl(p, v, l)
261
262
263static inline void
264__ixp4xx_outb(u8 value, u32 addr)
265{ 248{
266 u32 n, byte_enables, data; 249 u32 n, byte_enables, data;
267 n = addr % 4; 250 n = addr % 4;
@@ -270,15 +253,13 @@ __ixp4xx_outb(u8 value, u32 addr)
270 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); 253 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
271} 254}
272 255
273static inline void 256static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
274__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
275{ 257{
276 while (count--) 258 while (count--)
277 outb(*vaddr++, io_addr); 259 outb(*vaddr++, io_addr);
278} 260}
279 261
280static inline void 262static inline void outw(u16 value, u32 addr)
281__ixp4xx_outw(u16 value, u32 addr)
282{ 263{
283 u32 n, byte_enables, data; 264 u32 n, byte_enables, data;
284 n = addr % 4; 265 n = addr % 4;
@@ -287,28 +268,24 @@ __ixp4xx_outw(u16 value, u32 addr)
287 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); 268 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
288} 269}
289 270
290static inline void 271static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
291__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
292{ 272{
293 while (count--) 273 while (count--)
294 outw(cpu_to_le16(*vaddr++), io_addr); 274 outw(cpu_to_le16(*vaddr++), io_addr);
295} 275}
296 276
297static inline void 277static inline void outl(u32 value, u32 addr)
298__ixp4xx_outl(u32 value, u32 addr)
299{ 278{
300 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); 279 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
301} 280}
302 281
303static inline void 282static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
304__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
305{ 283{
306 while (count--) 284 while (count--)
307 outl(cpu_to_le32(*vaddr++), io_addr); 285 outl(cpu_to_le32(*vaddr++), io_addr);
308} 286}
309 287
310static inline u8 288static inline u8 inb(u32 addr)
311__ixp4xx_inb(u32 addr)
312{ 289{
313 u32 n, byte_enables, data; 290 u32 n, byte_enables, data;
314 n = addr % 4; 291 n = addr % 4;
@@ -319,15 +296,13 @@ __ixp4xx_inb(u32 addr)
319 return data >> (8*n); 296 return data >> (8*n);
320} 297}
321 298
322static inline void 299static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
323__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
324{ 300{
325 while (count--) 301 while (count--)
326 *vaddr++ = inb(io_addr); 302 *vaddr++ = inb(io_addr);
327} 303}
328 304
329static inline u16 305static inline u16 inw(u32 addr)
330__ixp4xx_inw(u32 addr)
331{ 306{
332 u32 n, byte_enables, data; 307 u32 n, byte_enables, data;
333 n = addr % 4; 308 n = addr % 4;
@@ -338,15 +313,13 @@ __ixp4xx_inw(u32 addr)
338 return data>>(8*n); 313 return data>>(8*n);
339} 314}
340 315
341static inline void 316static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
342__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
343{ 317{
344 while (count--) 318 while (count--)
345 *vaddr++ = le16_to_cpu(inw(io_addr)); 319 *vaddr++ = le16_to_cpu(inw(io_addr));
346} 320}
347 321
348static inline u32 322static inline u32 inl(u32 addr)
349__ixp4xx_inl(u32 addr)
350{ 323{
351 u32 data; 324 u32 data;
352 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) 325 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
@@ -355,8 +328,7 @@ __ixp4xx_inl(u32 addr)
355 return data; 328 return data;
356} 329}
357 330
358static inline void 331static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
359__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
360{ 332{
361 while (count--) 333 while (count--)
362 *vaddr++ = le32_to_cpu(inl(io_addr)); 334 *vaddr++ = le32_to_cpu(inl(io_addr));
@@ -368,12 +340,12 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
368#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ 340#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
369 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) 341 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
370 342
371static inline unsigned int 343#define ioread8(p) ioread8(p)
372__ixp4xx_ioread8(const void __iomem *addr) 344static inline unsigned int ioread8(const void __iomem *addr)
373{ 345{
374 unsigned long port = (unsigned long __force)addr; 346 unsigned long port = (unsigned long __force)addr;
375 if (__is_io_address(port)) 347 if (__is_io_address(port))
376 return (unsigned int)__ixp4xx_inb(port & PIO_MASK); 348 return (unsigned int)inb(port & PIO_MASK);
377 else 349 else
378#ifndef CONFIG_IXP4XX_INDIRECT_PCI 350#ifndef CONFIG_IXP4XX_INDIRECT_PCI
379 return (unsigned int)__raw_readb(port); 351 return (unsigned int)__raw_readb(port);
@@ -382,12 +354,12 @@ __ixp4xx_ioread8(const void __iomem *addr)
382#endif 354#endif
383} 355}
384 356
385static inline void 357#define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
386__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) 358static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
387{ 359{
388 unsigned long port = (unsigned long __force)addr; 360 unsigned long port = (unsigned long __force)addr;
389 if (__is_io_address(port)) 361 if (__is_io_address(port))
390 __ixp4xx_insb(port & PIO_MASK, vaddr, count); 362 insb(port & PIO_MASK, vaddr, count);
391 else 363 else
392#ifndef CONFIG_IXP4XX_INDIRECT_PCI 364#ifndef CONFIG_IXP4XX_INDIRECT_PCI
393 __raw_readsb(addr, vaddr, count); 365 __raw_readsb(addr, vaddr, count);
@@ -396,12 +368,12 @@ __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
396#endif 368#endif
397} 369}
398 370
399static inline unsigned int 371#define ioread16(p) ioread16(p)
400__ixp4xx_ioread16(const void __iomem *addr) 372static inline unsigned int ioread16(const void __iomem *addr)
401{ 373{
402 unsigned long port = (unsigned long __force)addr; 374 unsigned long port = (unsigned long __force)addr;
403 if (__is_io_address(port)) 375 if (__is_io_address(port))
404 return (unsigned int)__ixp4xx_inw(port & PIO_MASK); 376 return (unsigned int)inw(port & PIO_MASK);
405 else 377 else
406#ifndef CONFIG_IXP4XX_INDIRECT_PCI 378#ifndef CONFIG_IXP4XX_INDIRECT_PCI
407 return le16_to_cpu(__raw_readw((u32)port)); 379 return le16_to_cpu(__raw_readw((u32)port));
@@ -410,12 +382,13 @@ __ixp4xx_ioread16(const void __iomem *addr)
410#endif 382#endif
411} 383}
412 384
413static inline void 385#define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
414__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) 386static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
387 u32 count)
415{ 388{
416 unsigned long port = (unsigned long __force)addr; 389 unsigned long port = (unsigned long __force)addr;
417 if (__is_io_address(port)) 390 if (__is_io_address(port))
418 __ixp4xx_insw(port & PIO_MASK, vaddr, count); 391 insw(port & PIO_MASK, vaddr, count);
419 else 392 else
420#ifndef CONFIG_IXP4XX_INDIRECT_PCI 393#ifndef CONFIG_IXP4XX_INDIRECT_PCI
421 __raw_readsw(addr, vaddr, count); 394 __raw_readsw(addr, vaddr, count);
@@ -424,12 +397,12 @@ __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
424#endif 397#endif
425} 398}
426 399
427static inline unsigned int 400#define ioread32(p) ioread32(p)
428__ixp4xx_ioread32(const void __iomem *addr) 401static inline unsigned int ioread32(const void __iomem *addr)
429{ 402{
430 unsigned long port = (unsigned long __force)addr; 403 unsigned long port = (unsigned long __force)addr;
431 if (__is_io_address(port)) 404 if (__is_io_address(port))
432 return (unsigned int)__ixp4xx_inl(port & PIO_MASK); 405 return (unsigned int)inl(port & PIO_MASK);
433 else { 406 else {
434#ifndef CONFIG_IXP4XX_INDIRECT_PCI 407#ifndef CONFIG_IXP4XX_INDIRECT_PCI
435 return le32_to_cpu((__force __le32)__raw_readl(addr)); 408 return le32_to_cpu((__force __le32)__raw_readl(addr));
@@ -439,12 +412,13 @@ __ixp4xx_ioread32(const void __iomem *addr)
439 } 412 }
440} 413}
441 414
442static inline void 415#define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
443__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) 416static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
417 u32 count)
444{ 418{
445 unsigned long port = (unsigned long __force)addr; 419 unsigned long port = (unsigned long __force)addr;
446 if (__is_io_address(port)) 420 if (__is_io_address(port))
447 __ixp4xx_insl(port & PIO_MASK, vaddr, count); 421 insl(port & PIO_MASK, vaddr, count);
448 else 422 else
449#ifndef CONFIG_IXP4XX_INDIRECT_PCI 423#ifndef CONFIG_IXP4XX_INDIRECT_PCI
450 __raw_readsl(addr, vaddr, count); 424 __raw_readsl(addr, vaddr, count);
@@ -453,12 +427,12 @@ __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
453#endif 427#endif
454} 428}
455 429
456static inline void 430#define iowrite8(v, p) iowrite8(v, p)
457__ixp4xx_iowrite8(u8 value, void __iomem *addr) 431static inline void iowrite8(u8 value, void __iomem *addr)
458{ 432{
459 unsigned long port = (unsigned long __force)addr; 433 unsigned long port = (unsigned long __force)addr;
460 if (__is_io_address(port)) 434 if (__is_io_address(port))
461 __ixp4xx_outb(value, port & PIO_MASK); 435 outb(value, port & PIO_MASK);
462 else 436 else
463#ifndef CONFIG_IXP4XX_INDIRECT_PCI 437#ifndef CONFIG_IXP4XX_INDIRECT_PCI
464 __raw_writeb(value, port); 438 __raw_writeb(value, port);
@@ -467,12 +441,13 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr)
467#endif 441#endif
468} 442}
469 443
470static inline void 444#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
471__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) 445static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
446 u32 count)
472{ 447{
473 unsigned long port = (unsigned long __force)addr; 448 unsigned long port = (unsigned long __force)addr;
474 if (__is_io_address(port)) 449 if (__is_io_address(port))
475 __ixp4xx_outsb(port & PIO_MASK, vaddr, count); 450 outsb(port & PIO_MASK, vaddr, count);
476 else 451 else
477#ifndef CONFIG_IXP4XX_INDIRECT_PCI 452#ifndef CONFIG_IXP4XX_INDIRECT_PCI
478 __raw_writesb(addr, vaddr, count); 453 __raw_writesb(addr, vaddr, count);
@@ -481,12 +456,12 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
481#endif 456#endif
482} 457}
483 458
484static inline void 459#define iowrite16(v, p) iowrite16(v, p)
485__ixp4xx_iowrite16(u16 value, void __iomem *addr) 460static inline void iowrite16(u16 value, void __iomem *addr)
486{ 461{
487 unsigned long port = (unsigned long __force)addr; 462 unsigned long port = (unsigned long __force)addr;
488 if (__is_io_address(port)) 463 if (__is_io_address(port))
489 __ixp4xx_outw(value, port & PIO_MASK); 464 outw(value, port & PIO_MASK);
490 else 465 else
491#ifndef CONFIG_IXP4XX_INDIRECT_PCI 466#ifndef CONFIG_IXP4XX_INDIRECT_PCI
492 __raw_writew(cpu_to_le16(value), addr); 467 __raw_writew(cpu_to_le16(value), addr);
@@ -495,12 +470,13 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr)
495#endif 470#endif
496} 471}
497 472
498static inline void 473#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
499__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) 474static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
475 u32 count)
500{ 476{
501 unsigned long port = (unsigned long __force)addr; 477 unsigned long port = (unsigned long __force)addr;
502 if (__is_io_address(port)) 478 if (__is_io_address(port))
503 __ixp4xx_outsw(port & PIO_MASK, vaddr, count); 479 outsw(port & PIO_MASK, vaddr, count);
504 else 480 else
505#ifndef CONFIG_IXP4XX_INDIRECT_PCI 481#ifndef CONFIG_IXP4XX_INDIRECT_PCI
506 __raw_writesw(addr, vaddr, count); 482 __raw_writesw(addr, vaddr, count);
@@ -509,12 +485,12 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
509#endif 485#endif
510} 486}
511 487
512static inline void 488#define iowrite32(v, p) iowrite32(v, p)
513__ixp4xx_iowrite32(u32 value, void __iomem *addr) 489static inline void iowrite32(u32 value, void __iomem *addr)
514{ 490{
515 unsigned long port = (unsigned long __force)addr; 491 unsigned long port = (unsigned long __force)addr;
516 if (__is_io_address(port)) 492 if (__is_io_address(port))
517 __ixp4xx_outl(value, port & PIO_MASK); 493 outl(value, port & PIO_MASK);
518 else 494 else
519#ifndef CONFIG_IXP4XX_INDIRECT_PCI 495#ifndef CONFIG_IXP4XX_INDIRECT_PCI
520 __raw_writel((u32 __force)cpu_to_le32(value), addr); 496 __raw_writel((u32 __force)cpu_to_le32(value), addr);
@@ -523,12 +499,13 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
523#endif 499#endif
524} 500}
525 501
526static inline void 502#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
527__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) 503static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
504 u32 count)
528{ 505{
529 unsigned long port = (unsigned long __force)addr; 506 unsigned long port = (unsigned long __force)addr;
530 if (__is_io_address(port)) 507 if (__is_io_address(port))
531 __ixp4xx_outsl(port & PIO_MASK, vaddr, count); 508 outsl(port & PIO_MASK, vaddr, count);
532 else 509 else
533#ifndef CONFIG_IXP4XX_INDIRECT_PCI 510#ifndef CONFIG_IXP4XX_INDIRECT_PCI
534 __raw_writesl(addr, vaddr, count); 511 __raw_writesl(addr, vaddr, count);
@@ -537,25 +514,8 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
537#endif 514#endif
538} 515}
539 516
540#define ioread8(p) __ixp4xx_ioread8(p)
541#define ioread16(p) __ixp4xx_ioread16(p)
542#define ioread32(p) __ixp4xx_ioread32(p)
543
544#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
545#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
546#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
547
548#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
549#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
550#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
551
552#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
553#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
554#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
555
556#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) 517#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
557#define ioport_unmap(addr) 518#define ioport_unmap(addr)
558#endif // !CONFIG_PCI 519#endif /* CONFIG_PCI */
559
560#endif // __ASM_ARM_ARCH_IO_H
561 520
521#endif /* __ASM_ARM_ARCH_IO_H */