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authorKrzysztof Halasa <khc@pm.waw.pl>2009-09-04 23:59:49 -0400
committerDavid S. Miller <davem@davemloft.net>2009-09-07 04:56:49 -0400
commit5dbc46506a4f7b9f564bb7589a49ed32bc1caa15 (patch)
tree160ba16158671e2967e37f9d7feab8dbc2707141 /arch/arm/mach-ixp4xx
parent32e6a0c82e7a7991a02414d830f262e1f4db73e6 (diff)
IXP42x HSS support for setting internal clock rate
HSS usually uses external clocks, so it's not a big deal. Internal clock is used for direct DTE-DTE connections and when the DCE doesn't provide it's own clock. This also depends on the oscillator frequency. Intel seems to have calculated the clock register settings for 33.33 MHz (66.66 MHz timer base). Their settings seem quite suboptimal both in terms of average frequency (60 ppm is unacceptable for G.703 applications, their primary intended usage(?)) and jitter. Many (most?) platforms use a 33.333 MHz oscillator, a 10 ppm difference from Intel's base. Instead of creating static tables, I've created a procedure to program the HSS clock register. The register consists of 3 parts (A, B, C). The average frequency (= bit rate) is: 66.66x MHz / (A + (B + 1) / (C + 1)) The procedure aims at the closest average frequency, possibly at the cost of increased jitter. Nobody would be able to directly drive an unbufferred transmitter with a HSS anyway, and the frequency error is what it really counts. I've verified the above with an oscilloscope on IXP425. It seems IXP46x and possibly IXP43x use a bit different clock generation algorithm - it looks like the avg frequency is: (on IXP465) 66.66x MHz / (A + B / (C + 1)). Also they use much greater precomputed A and B - on IXP425 it would simply result in more jitter, but I don't know how does it work on IXP46x (perhaps 3 least significant bits aren't used?). Anyway it looks that they were aiming for exactly +60 ppm or -60 ppm, while <1 ppm is typically possible (with a synchronized clock, of course). The attached patch makes it possible to set almost any bit rate (my IXP425 533 MHz quits at > 22 Mb/s if a single port is used, and the minimum is ca. 65 Kb/s). This is independent of MVIP (multi-E1/T1 on one HSS) mode. Signed-off-by: Krzysztof HaƂasa <khc@pm.waw.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm/mach-ixp4xx')
-rw-r--r--arch/arm/mach-ixp4xx/common.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 1e93dfee7543..5083f03e9b5e 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -416,6 +416,7 @@ static struct clocksource clocksource_ixp4xx = {
416}; 416};
417 417
418unsigned long ixp4xx_timer_freq = FREQ; 418unsigned long ixp4xx_timer_freq = FREQ;
419EXPORT_SYMBOL(ixp4xx_timer_freq);
419static int __init ixp4xx_clocksource_init(void) 420static int __init ixp4xx_clocksource_init(void)
420{ 421{
421 clocksource_ixp4xx.mult = 422 clocksource_ixp4xx.mult =