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authorKrzysztof Hałasa <khc@pm.waw.pl>2010-03-26 11:38:52 -0400
committerJason Cooper <jason@lakedaemon.net>2012-11-21 22:36:30 -0500
commitf0cdb153292635203b3a0921c901dacf85d4ef1b (patch)
tree1efac5467dd39a0ee0ad7eae5f6dfdcad14a76bc /arch/arm/mach-ixp4xx
parent05cd3db0df6f6ac3083a9e9671dd1662053604df (diff)
IXP4xx: Always ioremap() Queue Manager MMIO region at boot.
It doesn't make much sense to map QMgr dynamically - we almost always need it and the static mapping will be needed for little-endian data-coherent operation (to make QMgr region value-coherent). Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Diffstat (limited to 'arch/arm/mach-ixp4xx')
-rw-r--r--arch/arm/mach-ixp4xx/common.c5
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h7
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/qmgr.h12
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_qmgr.c14
4 files changed, 17 insertions, 21 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fdf91a160884..acc0584377fc 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -67,6 +67,11 @@ static struct map_desc ixp4xx_io_desc[] __initdata = {
67 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), 67 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
68 .length = IXP4XX_PCI_CFG_REGION_SIZE, 68 .length = IXP4XX_PCI_CFG_REGION_SIZE,
69 .type = MT_DEVICE 69 .type = MT_DEVICE
70 }, { /* Queue Manager */
71 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
72 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
73 .length = IXP4XX_QMGR_REGION_SIZE,
74 .type = MT_DEVICE
70 }, 75 },
71#ifdef CONFIG_DEBUG_LL 76#ifdef CONFIG_DEBUG_LL
72 { /* Debug UART mapping */ 77 { /* Debug UART mapping */
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index eb68b61ce975..a24a8fe76604 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -30,19 +30,20 @@
30 * 30 *
31 * 0x50000000 0x10000000 ioremap'd EXP BUS 31 * 0x50000000 0x10000000 ioremap'd EXP BUS
32 * 32 *
33 * 0x6000000 0x00004000 ioremap'd QMgr 33 * 0x60000000 0x00004000 0xffbe7000 QMgr
34 * 34 *
35 * 0xC0000000 0x00001000 0xffbff000 PCI CFG 35 * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
36 * 36 *
37 * 0xC4000000 0x00001000 0xffbfe000 EXP CFG 37 * 0xC4000000 0x00001000 0xffbfe000 EXP CFG
38 * 38 *
39 * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals 39 * 0xC0000000 0x00001000 0xffbff000 PCI CFG
40 */ 40 */
41 41
42/* 42/*
43 * Queue Manager 43 * Queue Manager
44 */ 44 */
45#define IXP4XX_QMGR_BASE_PHYS (0x60000000) 45#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
46#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFFBE7000)
46#define IXP4XX_QMGR_REGION_SIZE (0x00004000) 47#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
47 48
48/* 49/*
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
index 9e7cad2d54cb..0a88d3b8e806 100644
--- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
@@ -86,7 +86,7 @@ void qmgr_release_queue(unsigned int queue);
86 86
87static inline void qmgr_put_entry(unsigned int queue, u32 val) 87static inline void qmgr_put_entry(unsigned int queue, u32 val)
88{ 88{
89 extern struct qmgr_regs __iomem *qmgr_regs; 89 const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
90#if DEBUG_QMGR 90#if DEBUG_QMGR
91 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ 91 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
92 92
@@ -99,7 +99,7 @@ static inline void qmgr_put_entry(unsigned int queue, u32 val)
99static inline u32 qmgr_get_entry(unsigned int queue) 99static inline u32 qmgr_get_entry(unsigned int queue)
100{ 100{
101 u32 val; 101 u32 val;
102 extern struct qmgr_regs __iomem *qmgr_regs; 102 const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
103 val = __raw_readl(&qmgr_regs->acc[queue][0]); 103 val = __raw_readl(&qmgr_regs->acc[queue][0]);
104#if DEBUG_QMGR 104#if DEBUG_QMGR
105 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ 105 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
@@ -112,14 +112,14 @@ static inline u32 qmgr_get_entry(unsigned int queue)
112 112
113static inline int __qmgr_get_stat1(unsigned int queue) 113static inline int __qmgr_get_stat1(unsigned int queue)
114{ 114{
115 extern struct qmgr_regs __iomem *qmgr_regs; 115 const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
116 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) 116 return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
117 >> ((queue & 7) << 2)) & 0xF; 117 >> ((queue & 7) << 2)) & 0xF;
118} 118}
119 119
120static inline int __qmgr_get_stat2(unsigned int queue) 120static inline int __qmgr_get_stat2(unsigned int queue)
121{ 121{
122 extern struct qmgr_regs __iomem *qmgr_regs; 122 const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
123 BUG_ON(queue >= HALF_QUEUES); 123 BUG_ON(queue >= HALF_QUEUES);
124 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) 124 return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
125 >> ((queue & 0xF) << 1)) & 0x3; 125 >> ((queue & 0xF) << 1)) & 0x3;
@@ -145,7 +145,7 @@ static inline int qmgr_stat_empty(unsigned int queue)
145 */ 145 */
146static inline int qmgr_stat_below_low_watermark(unsigned int queue) 146static inline int qmgr_stat_below_low_watermark(unsigned int queue)
147{ 147{
148 extern struct qmgr_regs __iomem *qmgr_regs; 148 const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
149 if (queue >= HALF_QUEUES) 149 if (queue >= HALF_QUEUES)
150 return (__raw_readl(&qmgr_regs->statne_h) >> 150 return (__raw_readl(&qmgr_regs->statne_h) >>
151 (queue - HALF_QUEUES)) & 0x01; 151 (queue - HALF_QUEUES)) & 0x01;
@@ -172,7 +172,7 @@ static inline int qmgr_stat_above_high_watermark(unsigned int queue)
172 */ 172 */
173static inline int qmgr_stat_full(unsigned int queue) 173static inline int qmgr_stat_full(unsigned int queue)
174{ 174{
175 extern struct qmgr_regs __iomem *qmgr_regs; 175 const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
176 if (queue >= HALF_QUEUES) 176 if (queue >= HALF_QUEUES)
177 return (__raw_readl(&qmgr_regs->statf_h) >> 177 return (__raw_readl(&qmgr_regs->statf_h) >>
178 (queue - HALF_QUEUES)) & 0x01; 178 (queue - HALF_QUEUES)) & 0x01;
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index 852f7c9f87d0..7c0584e0ab87 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -14,7 +14,7 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <mach/qmgr.h> 15#include <mach/qmgr.h>
16 16
17struct qmgr_regs __iomem *qmgr_regs; 17static const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
18static struct resource *mem_res; 18static struct resource *mem_res;
19static spinlock_t qmgr_lock; 19static spinlock_t qmgr_lock;
20static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ 20static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
@@ -32,7 +32,7 @@ void qmgr_set_irq(unsigned int queue, int src,
32 32
33 spin_lock_irqsave(&qmgr_lock, flags); 33 spin_lock_irqsave(&qmgr_lock, flags);
34 if (queue < HALF_QUEUES) { 34 if (queue < HALF_QUEUES) {
35 u32 __iomem *reg; 35 const u32 __iomem *reg;
36 int bit; 36 int bit;
37 BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL); 37 BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
38 reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */ 38 reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
@@ -293,12 +293,6 @@ static int qmgr_init(void)
293 if (mem_res == NULL) 293 if (mem_res == NULL)
294 return -EBUSY; 294 return -EBUSY;
295 295
296 qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
297 if (qmgr_regs == NULL) {
298 err = -ENOMEM;
299 goto error_map;
300 }
301
302 /* reset qmgr registers */ 296 /* reset qmgr registers */
303 for (i = 0; i < 4; i++) { 297 for (i = 0; i < 4; i++) {
304 __raw_writel(0x33333333, &qmgr_regs->stat1[i]); 298 __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
@@ -347,8 +341,6 @@ static int qmgr_init(void)
347error_irq2: 341error_irq2:
348 free_irq(IRQ_IXP4XX_QM1, NULL); 342 free_irq(IRQ_IXP4XX_QM1, NULL);
349error_irq: 343error_irq:
350 iounmap(qmgr_regs);
351error_map:
352 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); 344 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
353 return err; 345 return err;
354} 346}
@@ -359,7 +351,6 @@ static void qmgr_remove(void)
359 free_irq(IRQ_IXP4XX_QM2, NULL); 351 free_irq(IRQ_IXP4XX_QM2, NULL);
360 synchronize_irq(IRQ_IXP4XX_QM1); 352 synchronize_irq(IRQ_IXP4XX_QM1);
361 synchronize_irq(IRQ_IXP4XX_QM2); 353 synchronize_irq(IRQ_IXP4XX_QM2);
362 iounmap(qmgr_regs);
363 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); 354 release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
364} 355}
365 356
@@ -369,7 +360,6 @@ module_exit(qmgr_remove);
369MODULE_LICENSE("GPL v2"); 360MODULE_LICENSE("GPL v2");
370MODULE_AUTHOR("Krzysztof Halasa"); 361MODULE_AUTHOR("Krzysztof Halasa");
371 362
372EXPORT_SYMBOL(qmgr_regs);
373EXPORT_SYMBOL(qmgr_set_irq); 363EXPORT_SYMBOL(qmgr_set_irq);
374EXPORT_SYMBOL(qmgr_enable_irq); 364EXPORT_SYMBOL(qmgr_enable_irq);
375EXPORT_SYMBOL(qmgr_disable_irq); 365EXPORT_SYMBOL(qmgr_disable_irq);