locking, ARM: Annotate low level hw locks as raw

Annotate the low level hardware locks which must not be preempted.

In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 11 insertions, 11 deletions

diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 2131832ee6ba..1b5fe8705757 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -54,7 +54,7 @@ unsigned long ixp4xx_pci_reg_base = 0;
  * these transactions are atomic or we will end up
  * with corrupt data on the bus or in a driver.
  */
-static DEFINE_SPINLOCK(ixp4xx_pci_lock);
+static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
 
 /*
  * Read from PCI config space
@@ -62,10 +62,10 @@ static DEFINE_SPINLOCK(ixp4xx_pci_lock);
 static void crp_read(u32 ad_cbe, u32 *data)
 {
         unsigned long flags;
-        spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+        raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
         *PCI_CRP_AD_CBE = ad_cbe;
         *data = *PCI_CRP_RDATA;
-        spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 }
 
 /*
@@ -74,10 +74,10 @@ static void crp_read(u32 ad_cbe, u32 *data)
 static void crp_write(u32 ad_cbe, u32 data)
 { 
         unsigned long flags;
-        spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+        raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
         *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
         *PCI_CRP_WDATA = data;
-        spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 }
 
 static inline int check_master_abort(void)
@@ -101,7 +101,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
         int retval = 0;
         int i;
 
-        spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+        raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 
         *PCI_NP_AD = addr;
 
@@ -118,7 +118,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
         if(check_master_abort())
                 retval = 1;
 
-        spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
         return retval;
 }
 
@@ -127,7 +127,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
         unsigned long flags;
         int retval = 0;
 
-        spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+        raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 
         *PCI_NP_AD = addr;
 
@@ -140,7 +140,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
         if(check_master_abort())
                 retval = 1;
 
-        spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
         return retval;
 }
 
@@ -149,7 +149,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
         unsigned long flags;
         int retval = 0;
 
-        spin_lock_irqsave(&ixp4xx_pci_lock, flags);
+        raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 
         *PCI_NP_AD = addr;
 
@@ -162,7 +162,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
         if(check_master_abort())
                 retval = 1;
 
-        spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
         return retval;
 }