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authorKrzysztof Hałasa <khc@pm.waw.pl>2009-11-17 12:48:23 -0500
committerKrzysztof Hałasa <khc@pm.waw.pl>2009-12-05 10:58:41 -0500
commit8d3fdf31dd2066533861bb57ed7df1ae1b1f5fcc (patch)
tree5186d63c67dee5454348e55cf46d31053672d67d /arch/arm/mach-ixp4xx/dsmg600-pci.c
parenta8b7b34075f693632cd1483b817d4211c7a63257 (diff)
IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Diffstat (limited to 'arch/arm/mach-ixp4xx/dsmg600-pci.c')
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-pci.c57
1 files changed, 23 insertions, 34 deletions
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index 29a9e41fdf86..fa70fed462ba 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -22,53 +22,42 @@
22#include <asm/mach/pci.h> 22#include <asm/mach/pci.h>
23#include <asm/mach-types.h> 23#include <asm/mach-types.h>
24 24
25#define DSMG600_PCI_MAX_DEV 4 25#define MAX_DEV 4
26#define DSMG600_PCI_IRQ_LINES 3 26#define IRQ_LINES 3
27 27
28/* PCI controller GPIO to IRQ pin mappings */ 28/* PCI controller GPIO to IRQ pin mappings */
29#define DSMG600_PCI_INTA_PIN 11 29#define INTA 11
30#define DSMG600_PCI_INTB_PIN 10 30#define INTB 10
31#define DSMG600_PCI_INTC_PIN 9 31#define INTC 9
32#define DSMG600_PCI_INTD_PIN 8 32#define INTD 8
33#define DSMG600_PCI_INTE_PIN 7 33#define INTE 7
34#define DSMG600_PCI_INTF_PIN 6 34#define INTF 6
35
36#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11
37#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10
38#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9
39#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8
40#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
41#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
42 35
43void __init dsmg600_pci_preinit(void) 36void __init dsmg600_pci_preinit(void)
44{ 37{
45 set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); 38 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
46 set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); 39 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
47 set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 40 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
48 set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); 41 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
49 set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); 42 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
50 set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); 43 set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
51
52 ixp4xx_pci_preinit(); 44 ixp4xx_pci_preinit();
53} 45}
54 46
55static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 47static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
56{ 48{
57 static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] = 49 static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
58 { 50 { IXP4XX_GPIO_IRQ(INTE), -1, -1 },
59 { IRQ_DSMG600_PCI_INTE, -1, -1 }, 51 { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
60 { IRQ_DSMG600_PCI_INTA, -1, -1 }, 52 { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
61 { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD }, 53 IXP4XX_GPIO_IRQ(INTD) },
62 { IRQ_DSMG600_PCI_INTF, -1, -1 }, 54 { IXP4XX_GPIO_IRQ(INTF), -1, -1 },
63 }; 55 };
64 56
65 int irq = -1; 57 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
66 58 return pci_irq_table[slot - 1][pin - 1];
67 if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV &&
68 pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES)
69 irq = pci_irq_table[slot-1][pin-1];
70 59
71 return irq; 60 return -1;
72} 61}
73 62
74struct hw_pci __initdata dsmg600_pci = { 63struct hw_pci __initdata dsmg600_pci = {