IXP4xx: Extend PCI MMIO indirect address space to 1 GB.

IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using
the non-prefetch registers). Previously the available space depended on the CPU
variant, since one of the IXP43x platforms needed more than the usual 128 MB.
1 GB should be enough for everyone, and if not, we can trivially increase it.

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>

1 files changed, 11 insertions, 11 deletions

diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 264f4d59f898..9e5070da17ae 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI
         help
           IXP4xx provides two methods of accessing PCI memory space:
 
-          1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+          1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
              To access PCI via this space, we simply ioremap() the BAR
              into the kernel and we can use the standard read[bwl]/write[bwl]
              macros. This is the preferred method due to speed but it
-             limits the system to just 64MB of PCI memory. This can be 
+             limits the system to just 64MB of PCI memory. This can be
              problematic if using video cards and other memory-heavy devices.
-          
-          2) If > 64MB of memory space is required, the IXP4xx can be 
-             configured to use indirect registers to access PCI This allows 
-             for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 
-             The disadvantage of this is that every PCI access requires 
-             three local register accesses plus a spinlock, but in some 
-             cases the performance hit is acceptable. In addition, you cannot 
-             mmap() PCI devices in this case due to the indirect nature
-             of the PCI window.
+
+          2) If > 64MB of memory space is required, the IXP4xx can be
+             configured to use indirect registers to access the whole PCI
+             memory space. This currently allows for up to 1 GB (0x10000000
+             to 0x4FFFFFFF) of memory on the bus. The disadvantage of this
+             is that every PCI access requires three local register accesses
+             plus a spinlock, but in some cases the performance hit is
+             acceptable. In addition, you cannot mmap() PCI devices in this
+             case due to the indirect nature of the PCI window.
 
           By default, the direct method is used. Choose this option if you
           need to use the indirect method instead. If you don't know