diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-09-07 07:42:51 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-01 11:41:06 -0400 |
commit | db5b7169474882fabbd811a4cf5c1bae3157e677 (patch) | |
tree | b4218f6251b6719638f716fcc5aac62375903fe4 /arch/arm/mach-ixp2000 | |
parent | 40df2d1d8538865341a4cb9d4b7a375296517ad2 (diff) |
[ARM] Remove MT_DEVICE_IXP2000 and associated definitions
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same
PTE bit encoding as MT_DEVICE, so it's now redundant. Convert
MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ixp2000')
-rw-r--r-- | arch/arm/mach-ixp2000/core.c | 27 | ||||
-rw-r--r-- | arch/arm/mach-ixp2000/enp2611.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h | 8 |
3 files changed, 14 insertions, 27 deletions
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index a6a4f93085fd..628063ca31e6 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c | |||
@@ -84,64 +84,57 @@ static struct map_desc ixp2000_io_desc[] __initdata = { | |||
84 | .virtual = IXP2000_CAP_VIRT_BASE, | 84 | .virtual = IXP2000_CAP_VIRT_BASE, |
85 | .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), | 85 | .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), |
86 | .length = IXP2000_CAP_SIZE, | 86 | .length = IXP2000_CAP_SIZE, |
87 | .type = MT_DEVICE_IXP2000, | 87 | .type = MT_DEVICE, |
88 | }, { | 88 | }, { |
89 | .virtual = IXP2000_INTCTL_VIRT_BASE, | 89 | .virtual = IXP2000_INTCTL_VIRT_BASE, |
90 | .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), | 90 | .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), |
91 | .length = IXP2000_INTCTL_SIZE, | 91 | .length = IXP2000_INTCTL_SIZE, |
92 | .type = MT_DEVICE_IXP2000, | 92 | .type = MT_DEVICE, |
93 | }, { | 93 | }, { |
94 | .virtual = IXP2000_PCI_CREG_VIRT_BASE, | 94 | .virtual = IXP2000_PCI_CREG_VIRT_BASE, |
95 | .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), | 95 | .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), |
96 | .length = IXP2000_PCI_CREG_SIZE, | 96 | .length = IXP2000_PCI_CREG_SIZE, |
97 | .type = MT_DEVICE_IXP2000, | 97 | .type = MT_DEVICE, |
98 | }, { | 98 | }, { |
99 | .virtual = IXP2000_PCI_CSR_VIRT_BASE, | 99 | .virtual = IXP2000_PCI_CSR_VIRT_BASE, |
100 | .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), | 100 | .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), |
101 | .length = IXP2000_PCI_CSR_SIZE, | 101 | .length = IXP2000_PCI_CSR_SIZE, |
102 | .type = MT_DEVICE_IXP2000, | 102 | .type = MT_DEVICE, |
103 | }, { | 103 | }, { |
104 | .virtual = IXP2000_MSF_VIRT_BASE, | 104 | .virtual = IXP2000_MSF_VIRT_BASE, |
105 | .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), | 105 | .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), |
106 | .length = IXP2000_MSF_SIZE, | 106 | .length = IXP2000_MSF_SIZE, |
107 | .type = MT_DEVICE_IXP2000, | 107 | .type = MT_DEVICE, |
108 | }, { | 108 | }, { |
109 | .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, | 109 | .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, |
110 | .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), | 110 | .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), |
111 | .length = IXP2000_SCRATCH_RING_SIZE, | 111 | .length = IXP2000_SCRATCH_RING_SIZE, |
112 | .type = MT_DEVICE_IXP2000, | 112 | .type = MT_DEVICE, |
113 | }, { | 113 | }, { |
114 | .virtual = IXP2000_SRAM0_VIRT_BASE, | 114 | .virtual = IXP2000_SRAM0_VIRT_BASE, |
115 | .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), | 115 | .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), |
116 | .length = IXP2000_SRAM0_SIZE, | 116 | .length = IXP2000_SRAM0_SIZE, |
117 | .type = MT_DEVICE_IXP2000, | 117 | .type = MT_DEVICE, |
118 | }, { | 118 | }, { |
119 | .virtual = IXP2000_PCI_IO_VIRT_BASE, | 119 | .virtual = IXP2000_PCI_IO_VIRT_BASE, |
120 | .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), | 120 | .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), |
121 | .length = IXP2000_PCI_IO_SIZE, | 121 | .length = IXP2000_PCI_IO_SIZE, |
122 | .type = MT_DEVICE_IXP2000, | 122 | .type = MT_DEVICE, |
123 | }, { | 123 | }, { |
124 | .virtual = IXP2000_PCI_CFG0_VIRT_BASE, | 124 | .virtual = IXP2000_PCI_CFG0_VIRT_BASE, |
125 | .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), | 125 | .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), |
126 | .length = IXP2000_PCI_CFG0_SIZE, | 126 | .length = IXP2000_PCI_CFG0_SIZE, |
127 | .type = MT_DEVICE_IXP2000, | 127 | .type = MT_DEVICE, |
128 | }, { | 128 | }, { |
129 | .virtual = IXP2000_PCI_CFG1_VIRT_BASE, | 129 | .virtual = IXP2000_PCI_CFG1_VIRT_BASE, |
130 | .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), | 130 | .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), |
131 | .length = IXP2000_PCI_CFG1_SIZE, | 131 | .length = IXP2000_PCI_CFG1_SIZE, |
132 | .type = MT_DEVICE_IXP2000, | 132 | .type = MT_DEVICE, |
133 | } | 133 | } |
134 | }; | 134 | }; |
135 | 135 | ||
136 | void __init ixp2000_map_io(void) | 136 | void __init ixp2000_map_io(void) |
137 | { | 137 | { |
138 | /* | ||
139 | * On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that | ||
140 | * XCB=101 (to avoid triggering erratum #66), and given that | ||
141 | * this mode speeds up I/O accesses and we have write buffer | ||
142 | * flushes in the right places anyway, it doesn't hurt to use | ||
143 | * XCB=101 for all IXP2000s. | ||
144 | */ | ||
145 | iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); | 138 | iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); |
146 | 139 | ||
147 | /* Set slowport to 8-bit mode. */ | 140 | /* Set slowport to 8-bit mode. */ |
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c index c62ed655c1a7..8bb184dbc187 100644 --- a/arch/arm/mach-ixp2000/enp2611.c +++ b/arch/arm/mach-ixp2000/enp2611.c | |||
@@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = { | |||
70 | .virtual = ENP2611_CALEB_VIRT_BASE, | 70 | .virtual = ENP2611_CALEB_VIRT_BASE, |
71 | .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE), | 71 | .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE), |
72 | .length = ENP2611_CALEB_SIZE, | 72 | .length = ENP2611_CALEB_SIZE, |
73 | .type = MT_DEVICE_IXP2000, | 73 | .type = MT_DEVICE, |
74 | }, { | 74 | }, { |
75 | .virtual = ENP2611_PM3386_0_VIRT_BASE, | 75 | .virtual = ENP2611_PM3386_0_VIRT_BASE, |
76 | .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE), | 76 | .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE), |
77 | .length = ENP2611_PM3386_0_SIZE, | 77 | .length = ENP2611_PM3386_0_SIZE, |
78 | .type = MT_DEVICE_IXP2000, | 78 | .type = MT_DEVICE, |
79 | }, { | 79 | }, { |
80 | .virtual = ENP2611_PM3386_1_VIRT_BASE, | 80 | .virtual = ENP2611_PM3386_1_VIRT_BASE, |
81 | .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE), | 81 | .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE), |
82 | .length = ENP2611_PM3386_1_SIZE, | 82 | .length = ENP2611_PM3386_1_SIZE, |
83 | .type = MT_DEVICE_IXP2000, | 83 | .type = MT_DEVICE, |
84 | } | 84 | } |
85 | }; | 85 | }; |
86 | 86 | ||
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h index 19d80379a3e3..822f63f2f4a2 100644 --- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h +++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h | |||
@@ -41,13 +41,7 @@ | |||
41 | * Most of the registers are clumped in 4K regions spread throughout | 41 | * Most of the registers are clumped in 4K regions spread throughout |
42 | * the 0xc0000000 -> 0xc0100000 address range, but we just map in | 42 | * the 0xc0000000 -> 0xc0100000 address range, but we just map in |
43 | * the whole range using a single 1 MB section instead of small | 43 | * the whole range using a single 1 MB section instead of small |
44 | * 4K pages. This has two advantages for us: | 44 | * 4K pages. |
45 | * | ||
46 | * 1) We use only one TLB entry for large number of on-chip I/O devices. | ||
47 | * | ||
48 | * 2) We can easily set the Section attributes to XCB=101 on the IXP2400 | ||
49 | * as required per erratum #66. We accomplish this by using a | ||
50 | * new MT_IXP2000_DEVICE memory type with the bits set as required. | ||
51 | * | 45 | * |
52 | * CAP stands for CSR Access Proxy. | 46 | * CAP stands for CSR Access Proxy. |
53 | * | 47 | * |