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authorLennert Buytenhek <buytenh@wantstofly.org>2005-11-06 09:34:13 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-06 09:34:13 -0500
commit7240f1f183f085f6b7af44ec274b5b6123dfdead (patch)
treea68b0548c7c9adc78cdd3881029fdef1d8d53252 /arch/arm/mach-ixp2000/uengine.c
parent84613387cb60bc760a4588822cd61fb88e1d7fad (diff)
[ARM] 3114/1: use ixp2000_reg_wrb in ixp2000 uengine loader
Patch from Lennert Buytenhek Make the uengine loader use ixp2000_reg_wrb in the right places. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ixp2000/uengine.c')
-rw-r--r--arch/arm/mach-ixp2000/uengine.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mach-ixp2000/uengine.c b/arch/arm/mach-ixp2000/uengine.c
index 43e234349d4a..ec4e007a22ef 100644
--- a/arch/arm/mach-ixp2000/uengine.c
+++ b/arch/arm/mach-ixp2000/uengine.c
@@ -91,8 +91,8 @@ EXPORT_SYMBOL(ixp2000_uengine_csr_write);
91 91
92void ixp2000_uengine_reset(u32 uengine_mask) 92void ixp2000_uengine_reset(u32 uengine_mask)
93{ 93{
94 ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask); 94 ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
95 ixp2000_reg_write(IXP2000_RESET1, 0); 95 ixp2000_reg_wrb(IXP2000_RESET1, 0);
96} 96}
97EXPORT_SYMBOL(ixp2000_uengine_reset); 97EXPORT_SYMBOL(ixp2000_uengine_reset);
98 98
@@ -452,21 +452,20 @@ static int __init ixp2000_uengine_init(void)
452 /* 452 /*
453 * Reset microengines. 453 * Reset microengines.
454 */ 454 */
455 ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask); 455 ixp2000_uengine_reset(ixp2000_uengine_mask);
456 ixp2000_reg_write(IXP2000_RESET1, 0);
457 456
458 /* 457 /*
459 * Synchronise timestamp counters across all microengines. 458 * Synchronise timestamp counters across all microengines.
460 */ 459 */
461 value = ixp2000_reg_read(IXP2000_MISC_CONTROL); 460 value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
462 ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80); 461 ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
463 for (uengine = 0; uengine < 32; uengine++) { 462 for (uengine = 0; uengine < 32; uengine++) {
464 if (ixp2000_uengine_mask & (1 << uengine)) { 463 if (ixp2000_uengine_mask & (1 << uengine)) {
465 ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0); 464 ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
466 ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0); 465 ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
467 } 466 }
468 } 467 }
469 ixp2000_reg_write(IXP2000_MISC_CONTROL, value | 0x80); 468 ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80);
470 469
471 return 0; 470 return 0;
472} 471}