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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-05 11:14:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:48 -0400
commita09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch)
tree69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-ixp2000/include/mach
parenta1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff)
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ixp2000/include/mach')
-rw-r--r--arch/arm/mach-ixp2000/include/mach/debug-macro.S27
-rw-r--r--arch/arm/mach-ixp2000/include/mach/dma.h9
-rw-r--r--arch/arm/mach-ixp2000/include/mach/enp2611.h46
-rw-r--r--arch/arm/mach-ixp2000/include/mach/entry-macro.S60
-rw-r--r--arch/arm/mach-ixp2000/include/mach/gpio.h48
-rw-r--r--arch/arm/mach-ixp2000/include/mach/hardware.h44
-rw-r--r--arch/arm/mach-ixp2000/include/mach/io.h134
-rw-r--r--arch/arm/mach-ixp2000/include/mach/irqs.h207
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixdp2x00.h92
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixdp2x01.h57
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h457
-rw-r--r--arch/arm/mach-ixp2000/include/mach/memory.h34
-rw-r--r--arch/arm/mach-ixp2000/include/mach/platform.h152
-rw-r--r--arch/arm/mach-ixp2000/include/mach/system.h49
-rw-r--r--arch/arm/mach-ixp2000/include/mach/timex.h13
-rw-r--r--arch/arm/mach-ixp2000/include/mach/uncompress.h47
-rw-r--r--arch/arm/mach-ixp2000/include/mach/vmalloc.h20
17 files changed, 1496 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
new file mode 100644
index 000000000000..904ff56d2246
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -0,0 +1,27 @@
1/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0xc0000000 @ Physical base
18 movne \rx, #0xfe000000 @ virtual base
19 orrne \rx, \rx, #0x00f00000
20 orr \rx, \rx, #0x00030000
21#ifdef __ARMEB__
22 orr \rx, \rx, #0x00000003
23#endif
24 .endm
25
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp2000/include/mach/dma.h b/arch/arm/mach-ixp2000/include/mach/dma.h
new file mode 100644
index 000000000000..26063d60f622
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/dma.h
@@ -0,0 +1,9 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/dma.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h
new file mode 100644
index 000000000000..9ce3690061d5
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/enp2611.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/enp2611.h
3 *
4 * Register and other defines for Radisys ENP-2611
5 *
6 * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
7 * original version carries the following notices:
8 *
9 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
10 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
11 *
12 * Copyright (C) 2002 Intel Corp.
13 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef __ENP2611_H
22#define __ENP2611_H
23
24#define ENP2611_CALEB_PHYS_BASE 0xc5000000
25#define ENP2611_CALEB_VIRT_BASE 0xfe000000
26#define ENP2611_CALEB_SIZE 0x00100000
27
28#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000
29#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000
30#define ENP2611_PM3386_0_SIZE 0x00100000
31
32#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000
33#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000
34#define ENP2611_PM3386_1_SIZE 0x00100000
35
36#define ENP2611_GPIO_SCL 7
37#define ENP2611_GPIO_SDA 6
38
39#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4
40#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3
41#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2
42#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1
43#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0
44
45
46#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
new file mode 100644
index 000000000000..5850ffc8c751
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
@@ -0,0 +1,60 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IXP2000-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/irqs.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22
23 mov \irqnr, #0x0 @clear out irqnr as default
24 mov \base, #0xfe000000
25 orr \base, \base, #0x00e00000
26 orr \base, \base, #0x08
27 ldr \irqstat, [\base] @ get interrupts
28
29 cmp \irqstat, #0
30 beq 1001f
31
32 clz \irqnr, \irqstat
33 mov \base, #31
34 subs \irqnr, \base, \irqnr
35
36 /*
37 * We handle PCIA and PCIB here so we don't have an
38 * extra layer of code just to check these two bits.
39 */
40 cmp \irqnr, #IRQ_IXP2000_PCI
41 bne 1001f
42
43 mov \base, #0xfe000000
44 orr \base, \base, #0x00c00000
45 orr \base, \base, #0x00000100
46 orr \base, \base, #0x00000058
47 ldr \irqstat, [\base]
48
49 mov \tmp, #(1<<26)
50 tst \irqstat, \tmp
51 movne \irqnr, #IRQ_IXP2000_PCIA
52 bne 1001f
53
54 mov \tmp, #(1<<27)
55 tst \irqstat, \tmp
56 movne \irqnr, #IRQ_IXP2000_PCIB
57
581001:
59 .endm
60
diff --git a/arch/arm/mach-ixp2000/include/mach/gpio.h b/arch/arm/mach-ixp2000/include/mach/gpio.h
new file mode 100644
index 000000000000..4a88d2c33dac
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/gpio.h
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/gpio.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software, you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * IXP2000 GPIO in/out, edge/level detection for IRQs:
13 * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
14 * or both Falling-edge and Rising-edge.
15 * This must be called *before* the corresponding IRQ is registerd.
16 * Use this instead of directly setting the GPIO registers.
17 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
18 */
19#ifndef __ASM_ARCH_GPIO_H
20#define __ASM_ARCH_GPIO_H
21
22#ifndef __ASSEMBLY__
23
24#define GPIO_IN 0
25#define GPIO_OUT 1
26
27#define IXP2000_GPIO_LOW 0
28#define IXP2000_GPIO_HIGH 1
29
30extern void gpio_line_config(int line, int direction);
31
32static inline int gpio_line_get(int line)
33{
34 return (((*IXP2000_GPIO_PLR) >> line) & 1);
35}
36
37static inline void gpio_line_set(int line, int value)
38{
39 if (value == IXP2000_GPIO_HIGH) {
40 ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
41 } else if (value == IXP2000_GPIO_LOW) {
42 ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
43 }
44}
45
46#endif /* !__ASSEMBLY__ */
47
48#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
new file mode 100644
index 000000000000..f033de4e7493
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/hardware.h
@@ -0,0 +1,44 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/hardware.h
3 *
4 * Hardware definitions for IXP2400/2800 based systems
5 *
6 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@mvista.com>
9 *
10 * Copyright (C) 2001-2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#ifndef __ASM_ARCH_HARDWARE_H__
20#define __ASM_ARCH_HARDWARE_H__
21
22/*
23 * This needs to be platform-specific?
24 */
25#define PCIBIOS_MIN_IO 0x00000000
26#define PCIBIOS_MIN_MEM 0x00000000
27
28#include "ixp2000-regs.h" /* Chipset Registers */
29
30#define pcibios_assign_all_busses() 0
31
32/*
33 * Platform helper functions
34 */
35#include "platform.h"
36
37/*
38 * Platform-specific bits
39 */
40#include "enp2611.h" /* ENP-2611 */
41#include "ixdp2x00.h" /* IXDP2400/2800 */
42#include "ixdp2x01.h" /* IXDP2401/2801 */
43
44#endif /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
new file mode 100644
index 000000000000..859e584914d9
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -0,0 +1,134 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H
17
18#include <mach/hardware.h>
19
20#define IO_SPACE_LIMIT 0xffffffff
21#define __mem_pci(a) (a)
22
23/*
24 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
25 * transactions the other way round (MEM transactions don't have this
26 * issue), so if we want to support those models, we need to override
27 * the standard I/O functions.
28 *
29 * B0 and later have a bit that can be set to 1 to get the proper
30 * behavior for I/O transactions, which then allows us to use the
31 * standard I/O functions. This is what we do if the user does not
32 * explicitly ask for support for pre-B0.
33 */
34#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
35#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
36
37#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
38#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
39
40#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
41#define outw(v,p) __raw_writew((v),alignw(___io(p)))
42#define outl(v,p) __raw_writel((v),___io(p))
43
44#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
45#define inw(p) \
46 ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
47#define inl(p) \
48 ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
49
50#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
51#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
52#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
53
54#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
55#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
56#define insl(p,d,l) __raw_readsl(___io(p),d,l)
57
58#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
59
60#define ioread8(p) \
61 ({ \
62 unsigned int __v; \
63 \
64 if (__is_io_address(p)) { \
65 __v = __raw_readb(alignb(p)); \
66 } else { \
67 __v = __raw_readb(p); \
68 } \
69 \
70 __v; \
71 }) \
72
73#define ioread16(p) \
74 ({ \
75 unsigned int __v; \
76 \
77 if (__is_io_address(p)) { \
78 __v = __raw_readw(alignw(p)); \
79 } else { \
80 __v = le16_to_cpu(__raw_readw(p)); \
81 } \
82 \
83 __v; \
84 })
85
86#define ioread32(p) \
87 ({ \
88 unsigned int __v; \
89 \
90 if (__is_io_address(p)) { \
91 __v = __raw_readl(p); \
92 } else { \
93 __v = le32_to_cpu(__raw_readl(p)); \
94 } \
95 \
96 __v; \
97 })
98
99#define iowrite8(v,p) \
100 ({ \
101 if (__is_io_address(p)) { \
102 __raw_writeb((v), alignb(p)); \
103 } else { \
104 __raw_writeb((v), p); \
105 } \
106 })
107
108#define iowrite16(v,p) \
109 ({ \
110 if (__is_io_address(p)) { \
111 __raw_writew((v), alignw(p)); \
112 } else { \
113 __raw_writew(cpu_to_le16(v), p); \
114 } \
115 })
116
117#define iowrite32(v,p) \
118 ({ \
119 if (__is_io_address(p)) { \
120 __raw_writel((v), p); \
121 } else { \
122 __raw_writel(cpu_to_le32(v), p); \
123 } \
124 })
125
126#define ioport_map(port, nr) ___io(port)
127
128#define ioport_unmap(addr)
129#else
130#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
131#endif
132
133
134#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h
new file mode 100644
index 000000000000..bee96bcafdca
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/irqs.h
@@ -0,0 +1,207 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/irqs.h
3 *
4 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IRQS_H
16#define _IRQS_H
17
18/*
19 * Do NOT add #ifdef MACHINE_FOO in here.
20 * Simpy add your machine IRQs here and increase NR_IRQS if needed to
21 * hold your machine's IRQ table.
22 */
23
24/*
25 * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
26 * register has those bit reserved. We just mark those interrupts
27 * as invalid and this allows us to do mask/unmask with a single
28 * shift operation instead of having to map the IRQ number to
29 * a HW IRQ number.
30 */
31#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */
32#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
33#define IRQ_IXP2000_UART 2
34#define IRQ_IXP2000_GPIO 3
35#define IRQ_IXP2000_TIMER1 4
36#define IRQ_IXP2000_TIMER2 5
37#define IRQ_IXP2000_TIMER3 6
38#define IRQ_IXP2000_TIMER4 7
39#define IRQ_IXP2000_PMU 8
40#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
41#define IRQ_IXP2000_DMA1 10
42#define IRQ_IXP2000_DMA2 11
43#define IRQ_IXP2000_DMA3 12
44#define IRQ_IXP2000_PCI_DOORBELL 13
45#define IRQ_IXP2000_ME_ATTN 14
46#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
47#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
48#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */
49#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
50#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */
51#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */
52#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */
53#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
54#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */
55
56/* define generic GPIOs */
57#define IRQ_IXP2000_GPIO0 32
58#define IRQ_IXP2000_GPIO1 33
59#define IRQ_IXP2000_GPIO2 34
60#define IRQ_IXP2000_GPIO3 35
61#define IRQ_IXP2000_GPIO4 36
62#define IRQ_IXP2000_GPIO5 37
63#define IRQ_IXP2000_GPIO6 38
64#define IRQ_IXP2000_GPIO7 39
65
66/* split off the 2 PCI sources */
67#define IRQ_IXP2000_PCIA 40
68#define IRQ_IXP2000_PCIB 41
69
70/* Int sources from IRQ_ERROR_STATUS */
71#define IRQ_IXP2000_DRAM0_MIN_ERR 42
72#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
73#define IRQ_IXP2000_DRAM1_MIN_ERR 44
74#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
75#define IRQ_IXP2000_DRAM2_MIN_ERR 46
76#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
77/* 48-57 reserved */
78#define IRQ_IXP2000_SRAM0_ERR 58
79#define IRQ_IXP2000_SRAM1_ERR 59
80#define IRQ_IXP2000_SRAM2_ERR 60
81#define IRQ_IXP2000_SRAM3_ERR 61
82/* 62-65 reserved */
83#define IRQ_IXP2000_MEDIA_ERR 66
84#define IRQ_IXP2000_PCI_ERR 67
85#define IRQ_IXP2000_SP_INT 68
86
87#define NR_IXP2000_IRQS 69
88
89#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
90
91#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
92
93#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
94#define IXP2000_VALID_ERR_IRQ_MASK (\
95 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
96 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
97 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
98 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
99 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
100 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
101 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
102 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
103 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
104 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
105 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
106 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
107 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
108
109/*
110 * This allows for all the on-chip sources plus up to 32 CPLD based
111 * IRQs. Should be more than enough.
112 */
113#define IXP2000_BOARD_IRQS 32
114#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
115
116
117/*
118 * IXDP2400 specific IRQs
119 */
120#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
121#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
122#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
123#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
124#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
125#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
126#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
127#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
128
129#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
130#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
131
132/* IXDP2800 specific IRQs */
133#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
134#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
135#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
136#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
137#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
138#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
139
140#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
141#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
142
143/*
144 * IRQs on both IXDP2x01 boards
145 */
146#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
147#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
148#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
149#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
150#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
151#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
152#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
153#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
154#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
155#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
156#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
157#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
158#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
159#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
160#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
161#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
162
163#define IXDP2X01_VALID_IRQ_MASK ( \
164 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
165 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
166 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
167 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
168 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
169 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
170 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
171 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
172 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
173 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
174 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
175 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
176 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
177 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
178 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
179 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
180
181/*
182 * IXDP2401 specific IRQs
183 */
184#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
185#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
186
187#define IXDP2401_VALID_IRQ_MASK ( \
188 IXDP2X01_VALID_IRQ_MASK | \
189 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
190 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
191
192/*
193 * IXDP2801-specific IRQs
194 */
195#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
196#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
197#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
198
199#define IXDP2801_VALID_IRQ_MASK ( \
200 IXDP2X01_VALID_IRQ_MASK | \
201 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
202 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
203 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
204
205#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
206
207#endif /*_IRQS_H*/
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
new file mode 100644
index 000000000000..5df8479d9481
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
@@ -0,0 +1,92 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
3 *
4 * Register and other defines for IXDP2[48]00 platforms
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _IXDP2X00_H_
18#define _IXDP2X00_H_
19
20/*
21 * On board CPLD memory map
22 */
23#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
24#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000
25#define IXDP2X00_CPLD_SIZE 0x00100000
26
27
28#define IXDP2X00_CPLD_REG(x) \
29 (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
30
31/*
32 * IXDP2400 CPLD registers
33 */
34#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0)
35#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4)
36#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8)
37#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc)
38#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10)
39#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14)
40#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18)
41#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48)
42
43/*
44 * IXDP2800 CPLD registers
45 */
46#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0)
47#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140)
48
49
50#define IXDP2X00_GPIO_I2C_ENABLE 0x02
51#define IXDP2X00_GPIO_SCL 0x07
52#define IXDP2X00_GPIO_SDA 0x06
53
54/*
55 * PCI devfns for on-board devices. We need these to be able to
56 * properly translate IRQs and for device removal.
57 */
58#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */
59#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */
60#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */
61#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
62
63#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */
64#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */
65#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
66
67#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */
68#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */
69#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */
70#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */
71#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */
72
73#ifndef __ASSEMBLY__
74/*
75 * The master NPU is always PCI master.
76 */
77static inline unsigned int ixdp2x00_master_npu(void)
78{
79 return !!ixp2000_is_pcimaster();
80}
81
82/*
83 * Helper functions used by ixdp2400 and ixdp2800 specific code
84 */
85void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
86void ixdp2x00_slave_pci_postinit(void);
87void ixdp2x00_init_machine(void);
88void ixdp2x00_map_io(void);
89
90#endif
91
92#endif /*_IXDP2X00_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
new file mode 100644
index 000000000000..4c1f04083e54
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
@@ -0,0 +1,57 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
3 *
4 * Platform definitions for IXDP2X01 && IXDP2801 systems
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * Based on original code Copyright (c) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __IXDP2X01_H__
18#define __IXDP2X01_H__
19
20#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
21#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000
22#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
23
24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
25#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
26
27#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
28#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
29
30#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
31#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
32
33#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
34#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
35
36#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
37#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
38#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
39#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
40#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
41#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
42
43#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
44
45#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
46#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
47#define IXDP2X01_FLASH_WINDOW_BITS 25
48#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
49#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
50
51#define IXDP2X01_UART_CLK 1843200
52
53#define IXDP2X01_GPIO_I2C_ENABLE 0x02
54#define IXDP2X01_GPIO_SCL 0x07
55#define IXDP2X01_GPIO_SDA 0x06
56
57#endif /* __IXDP2x01_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
new file mode 100644
index 000000000000..19d80379a3e3
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
@@ -0,0 +1,457 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
3 *
4 * Chipset register definitions for IXP2400/2800 based systems.
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9 *
10 * Copyright (C) 2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _IXP2000_REGS_H_
19#define _IXP2000_REGS_H_
20
21/*
22 * IXP2000 linux memory map:
23 *
24 * virt phys size
25 * fb000000 db000000 16M PCI CFG1
26 * fc000000 da000000 16M PCI CFG0
27 * fd000000 d8000000 16M PCI I/O
28 * fe[0-7]00000 8M per-platform mappings
29 * fe900000 80000000 1M SRAM #0 (first MB)
30 * fea00000 cb400000 1M SCRATCH ring get/put
31 * feb00000 c8000000 1M MSF
32 * fec00000 df000000 1M PCI CSRs
33 * fed00000 de000000 1M PCI CREG
34 * fee00000 d6000000 1M INTCTL
35 * fef00000 c0000000 1M CAP
36 */
37
38/*
39 * Static I/O regions.
40 *
41 * Most of the registers are clumped in 4K regions spread throughout
42 * the 0xc0000000 -> 0xc0100000 address range, but we just map in
43 * the whole range using a single 1 MB section instead of small
44 * 4K pages. This has two advantages for us:
45 *
46 * 1) We use only one TLB entry for large number of on-chip I/O devices.
47 *
48 * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
49 * as required per erratum #66. We accomplish this by using a
50 * new MT_IXP2000_DEVICE memory type with the bits set as required.
51 *
52 * CAP stands for CSR Access Proxy.
53 *
54 * If you change the virtual address of this mapping, please propagate
55 * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
56 * address of the UART located in this region.
57 */
58
59#define IXP2000_CAP_PHYS_BASE 0xc0000000
60#define IXP2000_CAP_VIRT_BASE 0xfef00000
61#define IXP2000_CAP_SIZE 0x00100000
62
63/*
64 * Addresses for specific on-chip peripherals.
65 */
66#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
67#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
68#define IXP2000_UART_PHYS_BASE 0xc0030000
69#define IXP2000_UART_VIRT_BASE 0xfef30000
70#define IXP2000_TIMER_VIRT_BASE 0xfef20000
71#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
72#define IXP2000_GPIO_VIRT_BASE 0xfef10000
73
74/*
75 * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
76 * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
77 * entry-macro.S, so if you ever change these please propagate
78 * the change.
79 */
80#define IXP2000_INTCTL_PHYS_BASE 0xd6000000
81#define IXP2000_INTCTL_VIRT_BASE 0xfee00000
82#define IXP2000_INTCTL_SIZE 0x00100000
83
84#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
85#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000
86#define IXP2000_PCI_CREG_SIZE 0x00100000
87
88#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
89#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
90#define IXP2000_PCI_CSR_SIZE 0x00100000
91
92#define IXP2000_MSF_PHYS_BASE 0xc8000000
93#define IXP2000_MSF_VIRT_BASE 0xfeb00000
94#define IXP2000_MSF_SIZE 0x00100000
95
96#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
97#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
98#define IXP2000_SCRATCH_RING_SIZE 0x00100000
99
100#define IXP2000_SRAM0_PHYS_BASE 0x80000000
101#define IXP2000_SRAM0_VIRT_BASE 0xfe900000
102#define IXP2000_SRAM0_SIZE 0x00100000
103
104#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
105#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
106#define IXP2000_PCI_IO_SIZE 0x01000000
107
108#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
109#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
110#define IXP2000_PCI_CFG0_SIZE 0x01000000
111
112#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
113#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
114#define IXP2000_PCI_CFG1_SIZE 0x01000000
115
116/*
117 * Timers
118 */
119#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
120/* Timer control */
121#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
122#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
123#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
124#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
125/* Store initial value */
126#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
127#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
128#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
129#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
130/* Read current value */
131#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
132#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
133#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
134#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
135/* Clear associated timer interrupt */
136#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
137#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
138#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
139#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
140/* Timer watchdog enable for T4 */
141#define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
142
143#define WDT_ENABLE 0x00000001
144#define TIMER_DIVIDER_256 0x00000008
145#define TIMER_ENABLE 0x00000080
146#define IRQ_MASK_TIMER1 (1 << 4)
147
148/*
149 * Interrupt controller registers
150 */
151#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
152#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
153#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
154#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
155#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
156#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
157#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
158#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
159#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
160#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
161#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60)
162#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64)
163#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68)
164#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c)
165#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80)
166#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84)
167#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88)
168#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c)
169#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0)
170#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4)
171#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8)
172#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec)
173#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100)
174#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104)
175#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108)
176#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c)
177#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160)
178#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164)
179#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168)
180#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c)
181#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180)
182#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184)
183#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188)
184#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c)
185#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0)
186#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4)
187#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8)
188#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec)
189#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200)
190#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204)
191#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208)
192#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c)
193
194/*
195 * Mask of valid IRQs in the 32-bit IRQ register. We use
196 * this to mark certain IRQs as being invalid.
197 */
198#define IXP2000_VALID_IRQ_MASK 0x0f0fffff
199
200/*
201 * PCI config register access from core
202 */
203#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
204#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
205#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
206#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
207#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
208
209/*
210 * PCI CSRs
211 */
212#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
213
214/*
215 * PCI outbound interrupts
216 */
217#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
218#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
219/*
220 * PCI communications
221 */
222#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
223#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
224#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
225#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
226#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
227#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
228#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
229#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
230
231/*
232 * DMA engines
233 */
234#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
235#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
236#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
237#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
238#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
239#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
240#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
241#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
242#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
243#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
244#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
245#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
246#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
247#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
248#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
249#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
250#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
251#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
252#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
253/*
254 * Size masks for BARs
255 */
256#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
257#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
258/*
259 * Control and uEngine related
260 */
261#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
262#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
263#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
264#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
265#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
266#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
267/*
268 * Inbound PCI interrupt control
269 */
270#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
271#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
272
273#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
274#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */
275#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
276
277/* These are from the IRQ register in the PCI ISR register */
278#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
279#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
280#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
281#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
282#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
283
284#define IXP2000_PCI_RST_REL (1 << 2)
285#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
286#define CFG_PCI_BOOT_HOST (1 << 2)
287#define CFG_BOOT_PROM (1 << 1)
288
289/*
290 * SlowPort CSRs
291 *
292 * The slowport is used to access things like flash, SONET framer control
293 * ports, slave microprocessors, CPLDs, and others of chip memory mapped
294 * peripherals.
295 */
296#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
297
298#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
299#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
300#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
301#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
302#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
303#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
304#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
305#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
306#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
307#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
308#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
309
310/*
311 * CCR values.
312 * The CCR configures the clock division for the slowport interface.
313 */
314#define SLOWPORT_CCR_DIV_1 0x00
315#define SLOWPORT_CCR_DIV_2 0x01
316#define SLOWPORT_CCR_DIV_4 0x02
317#define SLOWPORT_CCR_DIV_6 0x03
318#define SLOWPORT_CCR_DIV_8 0x04
319#define SLOWPORT_CCR_DIV_10 0x05
320#define SLOWPORT_CCR_DIV_12 0x06
321#define SLOWPORT_CCR_DIV_14 0x07
322#define SLOWPORT_CCR_DIV_16 0x08
323#define SLOWPORT_CCR_DIV_18 0x09
324#define SLOWPORT_CCR_DIV_20 0x0a
325#define SLOWPORT_CCR_DIV_22 0x0b
326#define SLOWPORT_CCR_DIV_24 0x0c
327#define SLOWPORT_CCR_DIV_26 0x0d
328#define SLOWPORT_CCR_DIV_28 0x0e
329#define SLOWPORT_CCR_DIV_30 0x0f
330
331/*
332 * PCR values. PCR configure the mode of the interface.
333 */
334#define SLOWPORT_MODE_FLASH 0x00
335#define SLOWPORT_MODE_LUCENT 0x01
336#define SLOWPORT_MODE_PMC_SIERRA 0x02
337#define SLOWPORT_MODE_INTEL_UP 0x03
338#define SLOWPORT_MODE_MOTOROLA_UP 0x04
339
340/*
341 * ADC values. Defines data and address bus widths.
342 */
343#define SLOWPORT_ADDR_WIDTH_8 0x00
344#define SLOWPORT_ADDR_WIDTH_16 0x01
345#define SLOWPORT_ADDR_WIDTH_24 0x02
346#define SLOWPORT_ADDR_WIDTH_32 0x03
347#define SLOWPORT_DATA_WIDTH_8 0x00
348#define SLOWPORT_DATA_WIDTH_16 0x10
349#define SLOWPORT_DATA_WIDTH_24 0x20
350#define SLOWPORT_DATA_WIDTH_32 0x30
351
352/*
353 * Masks and shifts for various fields in the WTC and RTC registers.
354 */
355#define SLOWPORT_WRTC_MASK_HD 0x0003
356#define SLOWPORT_WRTC_MASK_PW 0x003c
357#define SLOWPORT_WRTC_MASK_SU 0x03c0
358
359#define SLOWPORT_WRTC_SHIFT_HD 0x00
360#define SLOWPORT_WRTC_SHIFT_SU 0x02
361#define SLOWPORT_WRTC_SHFIT_PW 0x06
362
363
364/*
365 * GPIO registers & GPIO interface.
366 */
367#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
368#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
369#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
370#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
371#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
372#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
373#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
374#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
375#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
376#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
377#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
378#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
379#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
380#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
381#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
382#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
383#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
384#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
385
386/*
387 * "Global" registers...whatever that's supposed to mean.
388 */
389#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
390#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
391
392#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
393#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
394#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
395#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
396#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
397#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
398#define IXP2000_MAJ_REV_MASK 0x000000F0
399#define IXP2000_MIN_REV_MASK 0x0000000F
400#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
401
402#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00)
403#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
404#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
405#define IXP2000_RESET0 GLOBAL_REG(0x0c)
406#define IXP2000_RESET1 GLOBAL_REG(0x10)
407#define IXP2000_CCR GLOBAL_REG(0x14)
408#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
409
410#define RSTALL (1 << 16)
411#define WDT_RESET_ENABLE 0x01000000
412
413
414/*
415 * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
416 * units, but the registers that differ between the two don't overlap,
417 * so we can have one register list for both.
418 */
419#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
420#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
421#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
422#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
423#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
424#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
425#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
426#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
427#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
428#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
429#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
430#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
431#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
432#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
433#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
434#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
435#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
436#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
437#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
438#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
439#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
440#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
441#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
442#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
443#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
444#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
445#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
446#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
447#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
448#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
449#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
450#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
451#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
452#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
453#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
454#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
455
456
457#endif /* _IXP2000_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
new file mode 100644
index 000000000000..241529a7c52d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/memory.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/memory.h
3 *
4 * Copyright (c) 2002 Intel Corp.
5 * Copyright (c) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PHYS_OFFSET UL(0x00000000)
17
18/*
19 * Virtual view <-> DMA view memory address translations
20 * virt_to_bus: Used to translate the virtual address to an
21 * address suitable to be passed to set_dma_addr
22 * bus_to_virt: Used to convert an address for DMA operations
23 * to an address that the kernel can use.
24 */
25#include <mach/ixp2000-regs.h>
26
27#define __virt_to_bus(v) \
28 (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
29
30#define __bus_to_virt(b) \
31 __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
32
33#endif
34
diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h
new file mode 100644
index 000000000000..42182c79ed90
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/platform.h
@@ -0,0 +1,152 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15
16#ifndef __ASSEMBLY__
17
18static inline unsigned long ixp2000_reg_read(volatile void *reg)
19{
20 return *((volatile unsigned long *)reg);
21}
22
23static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
24{
25 *((volatile unsigned long *)reg) = val;
26}
27
28/*
29 * On the IXP2400, we can't use XCB=000 due to chip bugs. We use
30 * XCB=101 instead, but that makes all I/O accesses bufferable. This
31 * is not a problem in general, but we do have to be slightly more
32 * careful because I/O writes are no longer automatically flushed out
33 * of the write buffer.
34 *
35 * In cases where we want to make sure that a write has been flushed
36 * out of the write buffer before we proceed, for example when masking
37 * a device interrupt before re-enabling IRQs in CPSR, we can use this
38 * function, ixp2000_reg_wrb, which performs a write, a readback, and
39 * issues a dummy instruction dependent on the value of the readback
40 * (mov rX, rX) to make sure that the readback has completed before we
41 * continue.
42 */
43static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
44{
45 unsigned long dummy;
46
47 *((volatile unsigned long *)reg) = val;
48
49 dummy = *((volatile unsigned long *)reg);
50 __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
51}
52
53/*
54 * Boards may multiplex different devices on the 2nd channel of
55 * the slowport interface that each need different configuration
56 * settings. For example, the IXDP2400 uses channel 2 on the interface
57 * to access the CPLD, the switch fabric card, and the media card. Each
58 * one needs a different mode so drivers must save/restore the mode
59 * before and after each operation.
60 *
61 * acquire_slowport(&your_config);
62 * ...
63 * do slowport operations
64 * ...
65 * release_slowport();
66 *
67 * Note that while you have the slowport, you are holding a spinlock,
68 * so your code should be written as if you explicitly acquired a lock.
69 *
70 * The configuration only affects device 2 on the slowport, so the
71 * MTD map driver does not acquire/release the slowport.
72 */
73struct slowport_cfg {
74 unsigned long CCR; /* Clock divide */
75 unsigned long WTC; /* Write Timing Control */
76 unsigned long RTC; /* Read Timing Control */
77 unsigned long PCR; /* Protocol Control Register */
78 unsigned long ADC; /* Address/Data Width Control */
79};
80
81
82void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
83void ixp2000_release_slowport(struct slowport_cfg *);
84
85/*
86 * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires
87 * tweaking of addresses in the MTD driver.
88 */
89static inline unsigned ixp2000_has_broken_slowport(void)
90{
91 unsigned long id = *IXP2000_PRODUCT_ID;
92 unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
93 IXP2000_MIN_PROD_TYPE_MASK);
94 return (((id_prod ==
95 /* fixed in IXP2400-B0 */
96 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
97 IXP2000_MIN_PROD_TYPE_IXP2400)) &&
98 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
99 ((id_prod ==
100 /* fixed in IXP2800-B0 */
101 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
102 IXP2000_MIN_PROD_TYPE_IXP2800)) &&
103 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
104 ((id_prod ==
105 /* fixed in IXP2850-B0 */
106 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
107 IXP2000_MIN_PROD_TYPE_IXP2850)) &&
108 ((id & IXP2000_MAJ_REV_MASK) == 0)));
109}
110
111static inline unsigned int ixp2000_has_flash(void)
112{
113 return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
114}
115
116static inline unsigned int ixp2000_is_pcimaster(void)
117{
118 return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
119}
120
121void ixp2000_map_io(void);
122void ixp2000_uart_init(void);
123void ixp2000_init_irq(void);
124void ixp2000_init_time(unsigned long);
125unsigned long ixp2000_gettimeoffset(void);
126
127struct pci_sys_data;
128
129u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
130void ixp2000_pci_preinit(void);
131int ixp2000_pci_setup(int, struct pci_sys_data*);
132struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
133int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
134int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
135
136/*
137 * Several of the IXP2000 systems have banked flash so we need to extend the
138 * flash_platform_data structure with some private pointers
139 */
140struct ixp2000_flash_data {
141 struct flash_platform_data *platform_data;
142 int nr_banks;
143 unsigned long (*bank_setup)(unsigned long);
144};
145
146struct ixp2000_i2c_pins {
147 unsigned long sda_pin;
148 unsigned long scl_pin;
149};
150
151
152#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
new file mode 100644
index 000000000000..2e9c68f95a24
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/system.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/system.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 * Copyricht (C) 2003-2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <mach/hardware.h>
13#include <asm/mach-types.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 local_irq_disable();
23
24 /*
25 * Reset flash banking register so that we are pointing at
26 * RedBoot bank.
27 */
28 if (machine_is_ixdp2401()) {
29 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
30 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
31 | IXDP2X01_CPLD_FLASH_INTERN));
32 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
33 }
34
35 /*
36 * On IXDP2801 we need to write this magic sequence to the CPLD
37 * to cause a complete reset of the CPU and all external devices
38 * and move the flash bank register back to 0.
39 */
40 if (machine_is_ixdp2801() || machine_is_ixdp28x5()) {
41 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
42
43 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
44 ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
45 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
46 }
47
48 ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
49}
diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h
new file mode 100644
index 000000000000..835e659f93d4
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/timex.h
@@ -0,0 +1,13 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/timex.h
3 *
4 * IXP2000 architecture timex specifications
5 */
6
7
8/*
9 * Default clock is 50MHz APB, but platform code can override this
10 */
11#define CLOCK_TICK_RATE 50000000
12
13
diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h
new file mode 100644
index 000000000000..ce363087df78
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/uncompress.h
3 *
4 *
5 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <linux/serial_reg.h>
18
19#define UART_BASE 0xc0030000
20
21#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x))
22
23#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */
24#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/
25#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/
26#define UARTIER PHYS(0x04) /* Interrupt enable reg */
27#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/
28#define UARTLCR PHYS(0x0c) /* Control reg */
29#define UARTSR PHYS(0x14) /* Status reg */
30
31
32static inline void putc(int c)
33{
34 int j = 0x1000;
35
36 while (--j && !(*UARTSR & UART_LSR_THRE))
37 barrier();
38
39 *UARTDR = c;
40}
41
42static inline void flush(void)
43{
44}
45
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d195e35aed3b
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/vmalloc.h
3 *
4 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 *
6 * Copyright 2002 Intel Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Just any arbitrary offset to the start of the vmalloc VM area: the
14 * current 8MB value just means that there will be a 8MB "hole" after the
15 * physical memory until the kernel virtual memory starts. That means that
16 * any out-of-bounds memory accesses will hopefully be caught.
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;)
19 */
20#define VMALLOC_END 0xfb000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 15:22:40 -0400