diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-09-18 18:17:36 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-25 05:25:41 -0400 |
commit | 7e9740b11529a0a69789fbe92d324f293e6266f6 (patch) | |
tree | 7ea94f603608744270756b56c668d658174a5b9b /arch/arm/mach-iop33x | |
parent | 0cb015f9dea8a40d82d170be1a4f39ff909890bf (diff) |
[ARM] 3821/1: iop3xx: switch iop32x/iop33x over to shared pci code
Switch the iop32x and iop33x code over to the common PCI implementation,
and remove the (nearly identical) iop32x and iop33x PCI implementations.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop33x')
-rw-r--r-- | arch/arm/mach-iop33x/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-iop33x/common.c | 22 | ||||
-rw-r--r-- | arch/arm/mach-iop33x/iq80331-pci.c | 45 | ||||
-rw-r--r-- | arch/arm/mach-iop33x/iq80332-pci.c | 45 | ||||
-rw-r--r-- | arch/arm/mach-iop33x/irq.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-iop33x/pci.c | 222 |
6 files changed, 8 insertions, 330 deletions
diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile index 7865923b0a60..6c74f13b1139 100644 --- a/arch/arm/mach-iop33x/Makefile +++ b/arch/arm/mach-iop33x/Makefile | |||
@@ -2,7 +2,7 @@ | |||
2 | # Makefile for the linux kernel. | 2 | # Makefile for the linux kernel. |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := common.o setup.o irq.o pci.o time.o | 5 | obj-y := setup.o irq.o time.o |
6 | obj-m := | 6 | obj-m := |
7 | obj-n := | 7 | obj-n := |
8 | obj- := | 8 | obj- := |
diff --git a/arch/arm/mach-iop33x/common.c b/arch/arm/mach-iop33x/common.c deleted file mode 100644 index dd75f2b8e74f..000000000000 --- a/arch/arm/mach-iop33x/common.c +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-iop33x/common.c | ||
3 | * | ||
4 | * Common routines shared across all IOP3xx implementations | ||
5 | * | ||
6 | * Author: Deepak Saxena <dsaxena@mvista.com> | ||
7 | * | ||
8 | * Copyright 2003 (c) MontaVista, Software, Inc. | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #include <linux/delay.h> | ||
16 | #include <asm/hardware.h> | ||
17 | |||
18 | /* | ||
19 | * Shared variables | ||
20 | */ | ||
21 | unsigned long iop3xx_pcibios_min_io = 0; | ||
22 | unsigned long iop3xx_pcibios_min_mem = 0; | ||
diff --git a/arch/arm/mach-iop33x/iq80331-pci.c b/arch/arm/mach-iop33x/iq80331-pci.c index 71adb12a9421..8b0bed5e2f91 100644 --- a/arch/arm/mach-iop33x/iq80331-pci.c +++ b/arch/arm/mach-iop33x/iq80331-pci.c | |||
@@ -57,51 +57,12 @@ iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) | |||
57 | return PCI_IRQ_TABLE_LOOKUP(1, 7); | 57 | return PCI_IRQ_TABLE_LOOKUP(1, 7); |
58 | } | 58 | } |
59 | 59 | ||
60 | static int iq80331_setup(int nr, struct pci_sys_data *sys) | ||
61 | { | ||
62 | struct resource *res; | ||
63 | |||
64 | if(nr != 0) | ||
65 | return 0; | ||
66 | |||
67 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
68 | if (!res) | ||
69 | panic("PCI: unable to alloc resources"); | ||
70 | |||
71 | res[0].start = IOP331_PCI_LOWER_IO_VA; | ||
72 | res[0].end = IOP331_PCI_UPPER_IO_VA; | ||
73 | res[0].name = "IQ80331 PCI I/O Space"; | ||
74 | res[0].flags = IORESOURCE_IO; | ||
75 | |||
76 | res[1].start = IOP331_PCI_LOWER_MEM_PA; | ||
77 | res[1].end = IOP331_PCI_UPPER_MEM_PA; | ||
78 | res[1].name = "IQ80331 PCI Memory Space"; | ||
79 | res[1].flags = IORESOURCE_MEM; | ||
80 | |||
81 | request_resource(&ioport_resource, &res[0]); | ||
82 | request_resource(&iomem_resource, &res[1]); | ||
83 | |||
84 | sys->mem_offset = IOP331_PCI_MEM_OFFSET; | ||
85 | sys->io_offset = IOP331_PCI_IO_OFFSET; | ||
86 | |||
87 | sys->resource[0] = &res[0]; | ||
88 | sys->resource[1] = &res[1]; | ||
89 | sys->resource[2] = NULL; | ||
90 | |||
91 | return 1; | ||
92 | } | ||
93 | |||
94 | static void iq80331_preinit(void) | ||
95 | { | ||
96 | iop331_init(); | ||
97 | } | ||
98 | |||
99 | static struct hw_pci iq80331_pci __initdata = { | 60 | static struct hw_pci iq80331_pci __initdata = { |
100 | .swizzle = pci_std_swizzle, | 61 | .swizzle = pci_std_swizzle, |
101 | .nr_controllers = 1, | 62 | .nr_controllers = 1, |
102 | .setup = iq80331_setup, | 63 | .setup = iop3xx_pci_setup, |
103 | .scan = iop331_scan_bus, | 64 | .scan = iop3xx_pci_scan_bus, |
104 | .preinit = iq80331_preinit, | 65 | .preinit = iop3xx_pci_preinit, |
105 | .map_irq = iq80331_map_irq | 66 | .map_irq = iq80331_map_irq |
106 | }; | 67 | }; |
107 | 68 | ||
diff --git a/arch/arm/mach-iop33x/iq80332-pci.c b/arch/arm/mach-iop33x/iq80332-pci.c index f3010f85b1a2..0de8aa748dd8 100644 --- a/arch/arm/mach-iop33x/iq80332-pci.c +++ b/arch/arm/mach-iop33x/iq80332-pci.c | |||
@@ -63,51 +63,12 @@ iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) | |||
63 | return PCI_IRQ_TABLE_LOOKUP(1, 7); | 63 | return PCI_IRQ_TABLE_LOOKUP(1, 7); |
64 | } | 64 | } |
65 | 65 | ||
66 | static int iq80332_setup(int nr, struct pci_sys_data *sys) | ||
67 | { | ||
68 | struct resource *res; | ||
69 | |||
70 | if(nr != 0) | ||
71 | return 0; | ||
72 | |||
73 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
74 | if (!res) | ||
75 | panic("PCI: unable to alloc resources"); | ||
76 | |||
77 | res[0].start = IOP331_PCI_LOWER_IO_VA; | ||
78 | res[0].end = IOP331_PCI_UPPER_IO_VA; | ||
79 | res[0].name = "IQ80332 PCI I/O Space"; | ||
80 | res[0].flags = IORESOURCE_IO; | ||
81 | |||
82 | res[1].start = IOP331_PCI_LOWER_MEM_PA; | ||
83 | res[1].end = IOP331_PCI_UPPER_MEM_PA; | ||
84 | res[1].name = "IQ80332 PCI Memory Space"; | ||
85 | res[1].flags = IORESOURCE_MEM; | ||
86 | |||
87 | request_resource(&ioport_resource, &res[0]); | ||
88 | request_resource(&iomem_resource, &res[1]); | ||
89 | |||
90 | sys->mem_offset = IOP331_PCI_MEM_OFFSET; | ||
91 | sys->io_offset = IOP331_PCI_IO_OFFSET; | ||
92 | |||
93 | sys->resource[0] = &res[0]; | ||
94 | sys->resource[1] = &res[1]; | ||
95 | sys->resource[2] = NULL; | ||
96 | |||
97 | return 1; | ||
98 | } | ||
99 | |||
100 | static void iq80332_preinit(void) | ||
101 | { | ||
102 | iop331_init(); | ||
103 | } | ||
104 | |||
105 | static struct hw_pci iq80332_pci __initdata = { | 66 | static struct hw_pci iq80332_pci __initdata = { |
106 | .swizzle = pci_std_swizzle, | 67 | .swizzle = pci_std_swizzle, |
107 | .nr_controllers = 1, | 68 | .nr_controllers = 1, |
108 | .setup = iq80332_setup, | 69 | .setup = iop3xx_pci_setup, |
109 | .scan = iop331_scan_bus, | 70 | .scan = iop3xx_pci_scan_bus, |
110 | .preinit = iq80332_preinit, | 71 | .preinit = iop3xx_pci_preinit, |
111 | .map_irq = iq80332_map_irq | 72 | .map_irq = iq80332_map_irq |
112 | }; | 73 | }; |
113 | 74 | ||
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 029fa78876a5..bcffc33a5be8 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c | |||
@@ -117,7 +117,7 @@ void __init iop331_init_irq(void) | |||
117 | intstr_write0(0); // treat all as IRQ | 117 | intstr_write0(0); // treat all as IRQ |
118 | intstr_write1(0); | 118 | intstr_write1(0); |
119 | if(machine_is_iq80331()) // all interrupts are inputs to chip | 119 | if(machine_is_iq80331()) // all interrupts are inputs to chip |
120 | *IOP331_PCIIRSR = 0x0f; | 120 | *IOP3XX_PCIIRSR = 0x0f; |
121 | 121 | ||
122 | for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) | 122 | for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) |
123 | { | 123 | { |
diff --git a/arch/arm/mach-iop33x/pci.c b/arch/arm/mach-iop33x/pci.c deleted file mode 100644 index bf6aba91b47d..000000000000 --- a/arch/arm/mach-iop33x/pci.c +++ /dev/null | |||
@@ -1,222 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-iop33x/pci.c | ||
3 | * | ||
4 | * PCI support for the Intel IOP331 chipset | ||
5 | * | ||
6 | * Author: Dave Jiang (dave.jiang@intel.com) | ||
7 | * Copyright (C) 2003, 2004 Intel Corp. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | */ | ||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/pci.h> | ||
16 | #include <linux/slab.h> | ||
17 | #include <linux/mm.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/ioport.h> | ||
20 | |||
21 | #include <asm/io.h> | ||
22 | #include <asm/irq.h> | ||
23 | #include <asm/system.h> | ||
24 | #include <asm/hardware.h> | ||
25 | #include <asm/mach/pci.h> | ||
26 | |||
27 | #include <asm/arch/iop331.h> | ||
28 | |||
29 | #undef DEBUG | ||
30 | #undef DEBUG1 | ||
31 | |||
32 | #ifdef DEBUG | ||
33 | #define DBG(x...) printk(x) | ||
34 | #else | ||
35 | #define DBG(x...) do { } while (0) | ||
36 | #endif | ||
37 | |||
38 | #ifdef DEBUG1 | ||
39 | #define DBG1(x...) printk(x) | ||
40 | #else | ||
41 | #define DBG1(x...) do { } while (0) | ||
42 | #endif | ||
43 | |||
44 | /* | ||
45 | * This routine builds either a type0 or type1 configuration command. If the | ||
46 | * bus is on the 80331 then a type0 made, else a type1 is created. | ||
47 | */ | ||
48 | static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where) | ||
49 | { | ||
50 | struct pci_sys_data *sys = bus->sysdata; | ||
51 | u32 addr; | ||
52 | |||
53 | if (sys->busnr == bus->number) | ||
54 | addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); | ||
55 | else | ||
56 | addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; | ||
57 | |||
58 | addr |= PCI_FUNC(devfn) << 8 | (where & ~3); | ||
59 | |||
60 | return addr; | ||
61 | } | ||
62 | |||
63 | /* | ||
64 | * This routine checks the status of the last configuration cycle. If an error | ||
65 | * was detected it returns a 1, else it returns a 0. The errors being checked | ||
66 | * are parity, master abort, target abort (master and target). These types of | ||
67 | * errors occure during a config cycle where there is no device, like during | ||
68 | * the discovery stage. | ||
69 | */ | ||
70 | static int iop331_pci_status(void) | ||
71 | { | ||
72 | unsigned int status; | ||
73 | int ret = 0; | ||
74 | |||
75 | /* | ||
76 | * Check the status registers. | ||
77 | */ | ||
78 | status = *IOP331_ATUSR; | ||
79 | if (status & 0xf900) | ||
80 | { | ||
81 | DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); | ||
82 | *IOP331_ATUSR = status & 0xf900; | ||
83 | ret = 1; | ||
84 | } | ||
85 | status = *IOP331_ATUISR; | ||
86 | if (status & 0x679f) | ||
87 | { | ||
88 | DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); | ||
89 | *IOP331_ATUISR = status & 0x679f; | ||
90 | ret = 1; | ||
91 | } | ||
92 | return ret; | ||
93 | } | ||
94 | |||
95 | /* | ||
96 | * Simply write the address register and read the configuration | ||
97 | * data. Note that the 4 nop's ensure that we are able to handle | ||
98 | * a delayed abort (in theory.) | ||
99 | */ | ||
100 | static inline u32 iop331_read(unsigned long addr) | ||
101 | { | ||
102 | u32 val; | ||
103 | |||
104 | __asm__ __volatile__( | ||
105 | "str %1, [%2]\n\t" | ||
106 | "ldr %0, [%3]\n\t" | ||
107 | "nop\n\t" | ||
108 | "nop\n\t" | ||
109 | "nop\n\t" | ||
110 | "nop\n\t" | ||
111 | : "=r" (val) | ||
112 | : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); | ||
113 | |||
114 | return val; | ||
115 | } | ||
116 | |||
117 | /* | ||
118 | * The read routines must check the error status of the last configuration | ||
119 | * cycle. If there was an error, the routine returns all hex f's. | ||
120 | */ | ||
121 | static int | ||
122 | iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where, | ||
123 | int size, u32 *value) | ||
124 | { | ||
125 | unsigned long addr = iop331_cfg_address(bus, devfn, where); | ||
126 | u32 val = iop331_read(addr) >> ((where & 3) * 8); | ||
127 | |||
128 | if( iop331_pci_status() ) | ||
129 | val = 0xffffffff; | ||
130 | |||
131 | *value = val; | ||
132 | |||
133 | return PCIBIOS_SUCCESSFUL; | ||
134 | } | ||
135 | |||
136 | static int | ||
137 | iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where, | ||
138 | int size, u32 value) | ||
139 | { | ||
140 | unsigned long addr = iop331_cfg_address(bus, devfn, where); | ||
141 | u32 val; | ||
142 | |||
143 | if (size != 4) { | ||
144 | val = iop331_read(addr); | ||
145 | if (!iop331_pci_status() == 0) | ||
146 | return PCIBIOS_SUCCESSFUL; | ||
147 | |||
148 | where = (where & 3) * 8; | ||
149 | |||
150 | if (size == 1) | ||
151 | val &= ~(0xff << where); | ||
152 | else | ||
153 | val &= ~(0xffff << where); | ||
154 | |||
155 | *IOP331_OCCDR = val | value << where; | ||
156 | } else { | ||
157 | asm volatile( | ||
158 | "str %1, [%2]\n\t" | ||
159 | "str %0, [%3]\n\t" | ||
160 | "nop\n\t" | ||
161 | "nop\n\t" | ||
162 | "nop\n\t" | ||
163 | "nop\n\t" | ||
164 | : | ||
165 | : "r" (value), "r" (addr), | ||
166 | "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); | ||
167 | } | ||
168 | |||
169 | return PCIBIOS_SUCCESSFUL; | ||
170 | } | ||
171 | |||
172 | static struct pci_ops iop331_ops = { | ||
173 | .read = iop331_read_config, | ||
174 | .write = iop331_write_config, | ||
175 | }; | ||
176 | |||
177 | /* | ||
178 | * When a PCI device does not exist during config cycles, the XScale gets a | ||
179 | * bus error instead of returning 0xffffffff. This handler simply returns. | ||
180 | */ | ||
181 | int | ||
182 | iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) | ||
183 | { | ||
184 | DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", | ||
185 | addr, fsr, regs->ARM_pc, regs->ARM_lr); | ||
186 | |||
187 | /* | ||
188 | * If it was an imprecise abort, then we need to correct the | ||
189 | * return address to be _after_ the instruction. | ||
190 | */ | ||
191 | if (fsr & (1 << 10)) | ||
192 | regs->ARM_pc += 4; | ||
193 | |||
194 | return 0; | ||
195 | } | ||
196 | |||
197 | /* | ||
198 | * Scan an IOP331 PCI bus. sys->bus defines which bus we scan. | ||
199 | */ | ||
200 | struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys) | ||
201 | { | ||
202 | return pci_scan_bus(sys->busnr, &iop331_ops, sys); | ||
203 | } | ||
204 | |||
205 | void iop331_init(void) | ||
206 | { | ||
207 | DBG1("PCI: Intel 80331 PCI init code.\n"); | ||
208 | DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD); | ||
209 | DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n", | ||
210 | *IOP331_OMWTVR0, | ||
211 | *IOP331_OIOWTVR); | ||
212 | DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1); | ||
213 | DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR); | ||
214 | DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0); | ||
215 | DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1); | ||
216 | DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR); | ||
217 | DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2); | ||
218 | DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3); | ||
219 | |||
220 | hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort"); | ||
221 | } | ||
222 | |||