[ARM] 4186/1: iop: remove cp6_enable/disable routines

This functionality is replaced by cp6_trap

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 0 insertions, 12 deletions

diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index effbe6b782d0..c65ea78a2427 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -24,44 +24,32 @@ static u32 iop33x_mask1;
 
 static inline void intctl0_write(u32 val)
 {
-        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
-        iop3xx_cp6_disable();
 }
 
 static inline void intctl1_write(u32 val)
 {
-        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
-        iop3xx_cp6_disable();
 }
 
 static inline void intstr0_write(u32 val)
 {
-        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
-        iop3xx_cp6_disable();
 }
 
 static inline void intstr1_write(u32 val)
 {
-        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
-        iop3xx_cp6_disable();
 }
 
 static inline void intbase_write(u32 val)
 {
-        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
-        iop3xx_cp6_disable();
 }
 
 static inline void intsize_write(u32 val)
 {
-        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
-        iop3xx_cp6_disable();
 }
 
 static void