diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2007-02-20 05:52:01 -0500 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-20 05:52:43 -0500 |
commit | e80a0e6e7ccdf64575d4384cb4172860422f5b81 (patch) | |
tree | 8960fa71eb73d0f1185e893192411cb873362738 /arch/arm/mach-iop33x/irq.c | |
parent | 3b0eb4a195a124567cd0dd6f700f8388def542c6 (diff) | |
parent | 3668b45d46f777b0773ef5ff49531c1144efb6dd (diff) |
[ARM] Merge remaining IOP code
Conflicts:
include/asm-arm/arch-at91rm9200/entry-macro.S
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop33x/irq.c')
-rw-r--r-- | arch/arm/mach-iop33x/irq.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index effbe6b782d0..c65ea78a2427 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c | |||
@@ -24,44 +24,32 @@ static u32 iop33x_mask1; | |||
24 | 24 | ||
25 | static inline void intctl0_write(u32 val) | 25 | static inline void intctl0_write(u32 val) |
26 | { | 26 | { |
27 | iop3xx_cp6_enable(); | ||
28 | asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); | 27 | asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); |
29 | iop3xx_cp6_disable(); | ||
30 | } | 28 | } |
31 | 29 | ||
32 | static inline void intctl1_write(u32 val) | 30 | static inline void intctl1_write(u32 val) |
33 | { | 31 | { |
34 | iop3xx_cp6_enable(); | ||
35 | asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); | 32 | asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); |
36 | iop3xx_cp6_disable(); | ||
37 | } | 33 | } |
38 | 34 | ||
39 | static inline void intstr0_write(u32 val) | 35 | static inline void intstr0_write(u32 val) |
40 | { | 36 | { |
41 | iop3xx_cp6_enable(); | ||
42 | asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); | 37 | asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); |
43 | iop3xx_cp6_disable(); | ||
44 | } | 38 | } |
45 | 39 | ||
46 | static inline void intstr1_write(u32 val) | 40 | static inline void intstr1_write(u32 val) |
47 | { | 41 | { |
48 | iop3xx_cp6_enable(); | ||
49 | asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); | 42 | asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); |
50 | iop3xx_cp6_disable(); | ||
51 | } | 43 | } |
52 | 44 | ||
53 | static inline void intbase_write(u32 val) | 45 | static inline void intbase_write(u32 val) |
54 | { | 46 | { |
55 | iop3xx_cp6_enable(); | ||
56 | asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); | 47 | asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); |
57 | iop3xx_cp6_disable(); | ||
58 | } | 48 | } |
59 | 49 | ||
60 | static inline void intsize_write(u32 val) | 50 | static inline void intsize_write(u32 val) |
61 | { | 51 | { |
62 | iop3xx_cp6_enable(); | ||
63 | asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); | 52 | asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); |
64 | iop3xx_cp6_disable(); | ||
65 | } | 53 | } |
66 | 54 | ||
67 | static void | 55 | static void |