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authorLennert Buytenhek <buytenh@wantstofly.org>2006-09-18 18:24:52 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-25 05:25:50 -0400
commitc680b77efe4542830bb170e1cc40db1c47c569bc (patch)
treeed79bf5cb4bab39e694690747c34cee8798c6d02 /arch/arm/mach-iop32x
parent7412b10f7967ef4210ed6f793004d23642dc5140 (diff)
[ARM] 3830/1: iop3xx: board support file cleanup
Revamp the iop3xx board support: move the support code for each iop board type into its own file, start using platform serial and platform physmap flash devices, switch to a per-board time tick rate, and get rid of the ARCH_EP80219 and STEPD config options by doing the relevant checks at run time. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop32x')
-rw-r--r--arch/arm/mach-iop32x/Kconfig7
-rw-r--r--arch/arm/mach-iop32x/Makefile6
-rw-r--r--arch/arm/mach-iop32x/common.c67
-rw-r--r--arch/arm/mach-iop32x/iq31244-mm.c46
-rw-r--r--arch/arm/mach-iop32x/iq31244-pci.c90
-rw-r--r--arch/arm/mach-iop32x/iq31244.c293
-rw-r--r--arch/arm/mach-iop32x/iq80321-mm.c46
-rw-r--r--arch/arm/mach-iop32x/iq80321-pci.c84
-rw-r--r--arch/arm/mach-iop32x/iq80321.c193
-rw-r--r--arch/arm/mach-iop32x/setup.c111
10 files changed, 489 insertions, 454 deletions
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index 21e3e8c8c2ad..ff8a77a8866e 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -16,13 +16,6 @@ config ARCH_IQ31244
16 Say Y here if you want to run your kernel on the Intel IQ31244 16 Say Y here if you want to run your kernel on the Intel IQ31244
17 evaluation kit for the IOP321 chipset. 17 evaluation kit for the IOP321 chipset.
18 18
19config ARCH_EP80219
20 bool "Enable support for EP80219"
21 select ARCH_IQ31244
22 help
23 Say Y here if you want to run your kernel on the Intel EP80219
24 evaluation kit for the Intel 80219 chipset (a IOP321 variant).
25
26endmenu 19endmenu
27 20
28endif 21endif
diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile
index ef561db20c9b..af1747ae392d 100644
--- a/arch/arm/mach-iop32x/Makefile
+++ b/arch/arm/mach-iop32x/Makefile
@@ -2,10 +2,10 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := common.o setup.o irq.o 5obj-y := irq.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o 10obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
11obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o 11obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c
deleted file mode 100644
index 9a17a081327d..000000000000
--- a/arch/arm/mach-iop32x/common.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/common.c
3 *
4 * Common routines shared across all IOP3xx implementations
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/delay.h>
16#include <asm/hardware.h>
17#include <asm/hardware/iop3xx.h>
18
19#ifdef CONFIG_ARCH_EP80219
20#include <linux/kernel.h>
21/*
22 * Default power-off for EP80219
23 */
24
25static inline void ep80219_send_to_pic(__u8 c) {
26}
27
28void ep80219_power_off(void)
29{
30 /*
31 * This function will send a SHUTDOWN_COMPLETE message to the PIC controller
32 * over I2C. We are not using the i2c subsystem since we are going to power
33 * off and it may be removed
34 */
35
36 /* Send the Address byte w/ the start condition */
37 *IOP3XX_IDBR1 = 0x60;
38 *IOP3XX_ICR1 = 0xE9;
39 mdelay(1);
40
41 /* Send the START_MSG byte w/ no start or stop condition */
42 *IOP3XX_IDBR1 = 0x0F;
43 *IOP3XX_ICR1 = 0xE8;
44 mdelay(1);
45
46 /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */
47 *IOP3XX_IDBR1 = 0x03;
48 *IOP3XX_ICR1 = 0xE8;
49 mdelay(1);
50
51 /* Send an ignored byte w/ stop condition */
52 *IOP3XX_IDBR1 = 0x00;
53 *IOP3XX_ICR1 = 0xEA;
54
55 while (1) ;
56}
57
58#include <linux/init.h>
59#include <linux/pm.h>
60
61static int __init ep80219_init(void)
62{
63 pm_power_off = ep80219_power_off;
64 return 0;
65}
66arch_initcall(ep80219_init);
67#endif
diff --git a/arch/arm/mach-iop32x/iq31244-mm.c b/arch/arm/mach-iop32x/iq31244-mm.c
deleted file mode 100644
index fba22d5d908f..000000000000
--- a/arch/arm/mach-iop32x/iq31244-mm.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop32x/iq31244-mm.c
3 *
4 * Low level memory initialization for iq80321 platform
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24#include <asm/hardware/iop3xx.h>
25
26
27/*
28 * IQ80321 specific IO mappings
29 *
30 * We use RedBoot's setup for the onboard devices.
31 */
32static struct map_desc iq31244_io_desc[] __initdata = {
33 { /* on-board devices */
34 .virtual = IQ31244_UART,
35 .pfn = __phys_to_pfn(IQ31244_UART),
36 .length = 0x00100000,
37 .type = MT_DEVICE
38 }
39};
40
41void __init iq31244_map_io(void)
42{
43 iop3xx_map_io();
44
45 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
46}
diff --git a/arch/arm/mach-iop32x/iq31244-pci.c b/arch/arm/mach-iop32x/iq31244-pci.c
deleted file mode 100644
index 605b79553747..000000000000
--- a/arch/arm/mach-iop32x/iq31244-pci.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/iq31244-pci.c
3 *
4 * PCI support for the Intel IQ31244 reference board
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/string.h>
18#include <linux/slab.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/mach/pci.h>
23#include <asm/mach-types.h>
24
25/*
26 * The following macro is used to lookup irqs in a standard table
27 * format for those systems that do not already have PCI
28 * interrupts properly routed. We assume 1 <= pin <= 4
29 */
30#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
31({ int _ctl_ = -1; \
32 unsigned int _idsel = idsel - minid; \
33 if (_idsel <= maxid) \
34 _ctl_ = pci_irq_table[_idsel][pin-1]; \
35 _ctl_; })
36
37#define INTA IRQ_IQ31244_INTA
38#define INTB IRQ_IQ31244_INTB
39#define INTC IRQ_IQ31244_INTC
40#define INTD IRQ_IQ31244_INTD
41
42#define INTE IRQ_IQ31244_I82546
43
44static inline int __init
45iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
46{
47 static int pci_irq_table[][4] = {
48 /*
49 * PCI IDSEL/INTPIN->INTLINE
50 * A B C D
51 */
52#ifdef CONFIG_ARCH_EP80219
53 {INTB, INTB, INTB, INTB}, /* CFlash */
54 {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */
55 {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
56 {INTC, INTC, INTC, INTC}, /* SATA */
57#else
58 {INTB, INTB, INTB, INTB}, /* CFlash */
59 {INTC, INTC, INTC, INTC}, /* SATA */
60 {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
61 {INTE, INTE, INTE, INTE}, /* 82546 GigE */
62#endif // CONFIG_ARCH_EP80219
63 };
64
65 BUG_ON(pin < 1 || pin > 4);
66
67 return PCI_IRQ_TABLE_LOOKUP(0, 7);
68}
69
70static struct hw_pci iq31244_pci __initdata = {
71 .swizzle = pci_std_swizzle,
72 .nr_controllers = 1,
73 .setup = iop3xx_pci_setup,
74 .scan = iop3xx_pci_scan_bus,
75 .preinit = iop3xx_pci_preinit,
76 .map_irq = iq31244_map_irq
77};
78
79static int __init iq31244_pci_init(void)
80{
81 if (machine_is_iq31244())
82 pci_common_init(&iq31244_pci);
83 return 0;
84}
85
86subsys_initcall(iq31244_pci_init);
87
88
89
90
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
new file mode 100644
index 000000000000..88b77d32b0ac
--- /dev/null
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -0,0 +1,293 @@
1/*
2 * arch/arm/mach-iop32x/iq31244.c
3 *
4 * Board support code for the Intel EP80219 and IQ31244 platforms.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 * Copyright (C) 2004 Intel Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/pm.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <linux/mtd/physmap.h>
28#include <linux/platform_device.h>
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/pci.h>
35#include <asm/mach/time.h>
36#include <asm/mach-types.h>
37#include <asm/page.h>
38#include <asm/pgtable.h>
39
40
41/*
42 * The EP80219 and IQ31244 use the same machine ID. To find out
43 * which of the two we're running on, we look at the processor ID.
44 */
45static int is_80219(void)
46{
47 extern int processor_id;
48 return !!((processor_id & 0xffffffe0) == 0x69052e20);
49}
50
51
52/*
53 * EP80219/IQ31244 timer tick configuration.
54 */
55static void __init iq31244_timer_init(void)
56{
57 if (is_80219()) {
58 /* 33.333 MHz crystal. */
59 iop3xx_init_time(200000000);
60 } else {
61 /* 33.000 MHz crystal. */
62 iop3xx_init_time(198000000);
63 }
64}
65
66static struct sys_timer iq31244_timer = {
67 .init = iq31244_timer_init,
68 .offset = iop3xx_gettimeoffset,
69};
70
71
72/*
73 * IQ31244 I/O.
74 */
75static struct map_desc iq31244_io_desc[] __initdata = {
76 { /* on-board devices */
77 .virtual = IQ31244_UART,
78 .pfn = __phys_to_pfn(IQ31244_UART),
79 .length = 0x00100000,
80 .type = MT_DEVICE,
81 },
82};
83
84void __init iq31244_map_io(void)
85{
86 iop3xx_map_io();
87 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
88}
89
90
91/*
92 * EP80219/IQ31244 PCI.
93 */
94static inline int __init
95ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
96{
97 int irq;
98
99 if (slot == 0) {
100 /* CFlash */
101 irq = IRQ_IOP321_XINT1;
102 } else if (slot == 1) {
103 /* 82551 Pro 100 */
104 irq = IRQ_IOP321_XINT0;
105 } else if (slot == 2) {
106 /* PCI-X Slot */
107 irq = IRQ_IOP321_XINT3;
108 } else if (slot == 3) {
109 /* SATA */
110 irq = IRQ_IOP321_XINT2;
111 } else {
112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
113 "device PCI:%d:%d:%d\n", dev->bus->number,
114 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
115 irq = -1;
116 }
117
118 return irq;
119}
120
121static struct hw_pci ep80219_pci __initdata = {
122 .swizzle = pci_std_swizzle,
123 .nr_controllers = 1,
124 .setup = iop3xx_pci_setup,
125 .preinit = iop3xx_pci_preinit,
126 .scan = iop3xx_pci_scan_bus,
127 .map_irq = ep80219_pci_map_irq,
128};
129
130static inline int __init
131iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
132{
133 int irq;
134
135 if (slot == 0) {
136 /* CFlash */
137 irq = IRQ_IOP321_XINT1;
138 } else if (slot == 1) {
139 /* SATA */
140 irq = IRQ_IOP321_XINT2;
141 } else if (slot == 2) {
142 /* PCI-X Slot */
143 irq = IRQ_IOP321_XINT3;
144 } else if (slot == 3) {
145 /* 82546 GigE */
146 irq = IRQ_IOP321_XINT0;
147 } else {
148 printk(KERN_ERR "iq31244_pci_map_irq() called for unknown "
149 "device PCI:%d:%d:%d\n", dev->bus->number,
150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
151 irq = -1;
152 }
153
154 return irq;
155}
156
157static struct hw_pci iq31244_pci __initdata = {
158 .swizzle = pci_std_swizzle,
159 .nr_controllers = 1,
160 .setup = iop3xx_pci_setup,
161 .preinit = iop3xx_pci_preinit,
162 .scan = iop3xx_pci_scan_bus,
163 .map_irq = iq31244_pci_map_irq,
164};
165
166static int __init iq31244_pci_init(void)
167{
168 if (machine_is_iq31244()) {
169 if (is_80219()) {
170 pci_common_init(&ep80219_pci);
171 } else {
172 pci_common_init(&iq31244_pci);
173 }
174 }
175
176 return 0;
177}
178
179subsys_initcall(iq31244_pci_init);
180
181
182/*
183 * IQ31244 machine initialisation.
184 */
185static struct physmap_flash_data iq31244_flash_data = {
186 .width = 2,
187};
188
189static struct resource iq31244_flash_resource = {
190 .start = 0xf0000000,
191 .end = 0xf07fffff,
192 .flags = IORESOURCE_MEM,
193};
194
195static struct platform_device iq31244_flash_device = {
196 .name = "physmap-flash",
197 .id = 0,
198 .dev = {
199 .platform_data = &iq31244_flash_data,
200 },
201 .num_resources = 1,
202 .resource = &iq31244_flash_resource,
203};
204
205static struct plat_serial8250_port iq31244_serial_port[] = {
206 {
207 .mapbase = IQ31244_UART,
208 .membase = (char *)IQ31244_UART,
209 .irq = IRQ_IOP321_XINT1,
210 .flags = UPF_SKIP_TEST,
211 .iotype = UPIO_MEM,
212 .regshift = 0,
213 .uartclk = 1843200,
214 },
215 { },
216};
217
218static struct resource iq31244_uart_resource = {
219 .start = IQ31244_UART,
220 .end = IQ31244_UART + 7,
221 .flags = IORESOURCE_MEM,
222};
223
224static struct platform_device iq31244_serial_device = {
225 .name = "serial8250",
226 .id = PLAT8250_DEV_PLATFORM,
227 .dev = {
228 .platform_data = iq31244_serial_port,
229 },
230 .num_resources = 1,
231 .resource = &iq31244_uart_resource,
232};
233
234/*
235 * This function will send a SHUTDOWN_COMPLETE message to the PIC
236 * controller over I2C. We are not using the i2c subsystem since
237 * we are going to power off and it may be removed
238 */
239void ep80219_power_off(void)
240{
241 /*
242 * Send the Address byte w/ the start condition
243 */
244 *IOP3XX_IDBR1 = 0x60;
245 *IOP3XX_ICR1 = 0xE9;
246 mdelay(1);
247
248 /*
249 * Send the START_MSG byte w/ no start or stop condition
250 */
251 *IOP3XX_IDBR1 = 0x0F;
252 *IOP3XX_ICR1 = 0xE8;
253 mdelay(1);
254
255 /*
256 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
257 * stop condition
258 */
259 *IOP3XX_IDBR1 = 0x03;
260 *IOP3XX_ICR1 = 0xE8;
261 mdelay(1);
262
263 /*
264 * Send an ignored byte w/ stop condition
265 */
266 *IOP3XX_IDBR1 = 0x00;
267 *IOP3XX_ICR1 = 0xEA;
268
269 while (1)
270 ;
271}
272
273static void __init iq31244_init_machine(void)
274{
275 platform_device_register(&iop3xx_i2c0_device);
276 platform_device_register(&iop3xx_i2c1_device);
277 platform_device_register(&iq31244_flash_device);
278 platform_device_register(&iq31244_serial_device);
279
280 if (is_80219())
281 pm_power_off = ep80219_power_off;
282}
283
284MACHINE_START(IQ31244, "Intel IQ31244")
285 /* Maintainer: Intel Corp. */
286 .phys_io = IQ31244_UART,
287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
288 .boot_params = 0xa0000100,
289 .map_io = iq31244_map_io,
290 .init_irq = iop321_init_irq,
291 .timer = &iq31244_timer,
292 .init_machine = iq31244_init_machine,
293MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321-mm.c b/arch/arm/mach-iop32x/iq80321-mm.c
deleted file mode 100644
index b6a3079ad29e..000000000000
--- a/arch/arm/mach-iop32x/iq80321-mm.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop32x/iq80321-mm.c
3 *
4 * Low level memory initialization for iq80321 platform
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24#include <asm/hardware/iop3xx.h>
25
26
27/*
28 * IQ80321 specific IO mappings
29 *
30 * We use RedBoot's setup for the onboard devices.
31 */
32static struct map_desc iq80321_io_desc[] __initdata = {
33 { /* on-board devices */
34 .virtual = IQ80321_UART,
35 .pfn = __phys_to_pfn(IQ80321_UART),
36 .length = 0x00100000,
37 .type = MT_DEVICE
38 }
39};
40
41void __init iq80321_map_io(void)
42{
43 iop3xx_map_io();
44
45 iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
46}
diff --git a/arch/arm/mach-iop32x/iq80321-pci.c b/arch/arm/mach-iop32x/iq80321-pci.c
deleted file mode 100644
index cedc37b968b7..000000000000
--- a/arch/arm/mach-iop32x/iq80321-pci.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/iq80321-pci.c
3 *
4 * PCI support for the Intel IQ80321 reference board
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/string.h>
18#include <linux/slab.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/mach/pci.h>
23#include <asm/mach-types.h>
24
25/*
26 * The following macro is used to lookup irqs in a standard table
27 * format for those systems that do not already have PCI
28 * interrupts properly routed. We assume 1 <= pin <= 4
29 */
30#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
31({ int _ctl_ = -1; \
32 unsigned int _idsel = idsel - minid; \
33 if (_idsel <= maxid) \
34 _ctl_ = pci_irq_table[_idsel][pin-1]; \
35 _ctl_; })
36
37#define INTA IRQ_IQ80321_INTA
38#define INTB IRQ_IQ80321_INTB
39#define INTC IRQ_IQ80321_INTC
40#define INTD IRQ_IQ80321_INTD
41
42#define INTE IRQ_IQ80321_I82544
43
44static inline int __init
45iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
46{
47 static int pci_irq_table[][4] = {
48 /*
49 * PCI IDSEL/INTPIN->INTLINE
50 * A B C D
51 */
52 {INTE, INTE, INTE, INTE}, /* Gig-E */
53 {-1, -1, -1, -1}, /* Unused */
54 {INTC, INTD, INTA, INTB}, /* PCI-X Slot */
55 {-1, -1, -1, -1},
56 };
57
58 BUG_ON(pin < 1 || pin > 4);
59
60// return PCI_IRQ_TABLE_LOOKUP(4, 7);
61 return pci_irq_table[idsel%4][pin-1];
62}
63
64static struct hw_pci iq80321_pci __initdata = {
65 .swizzle = pci_std_swizzle,
66 .nr_controllers = 1,
67 .setup = iop3xx_pci_setup,
68 .scan = iop3xx_pci_scan_bus,
69 .preinit = iop3xx_pci_preinit,
70 .map_irq = iq80321_map_irq
71};
72
73static int __init iq80321_pci_init(void)
74{
75 if (machine_is_iq80321())
76 pci_common_init(&iq80321_pci);
77 return 0;
78}
79
80subsys_initcall(iq80321_pci_init);
81
82
83
84
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
new file mode 100644
index 000000000000..3c9b86271759
--- /dev/null
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -0,0 +1,193 @@
1/*
2 * arch/arm/mach-iop32x/iq80321.c
3 *
4 * Board support code for the Intel IQ80321 platform.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/string.h>
21#include <linux/slab.h>
22#include <linux/serial_core.h>
23#include <linux/serial_8250.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26#include <asm/hardware.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/pci.h>
32#include <asm/mach/time.h>
33#include <asm/mach-types.h>
34#include <asm/page.h>
35#include <asm/pgtable.h>
36
37/*
38 * IQ80321 timer tick configuration.
39 */
40static void __init iq80321_timer_init(void)
41{
42 /* 33.333 MHz crystal. */
43 iop3xx_init_time(200000000);
44}
45
46static struct sys_timer iq80321_timer = {
47 .init = iq80321_timer_init,
48 .offset = iop3xx_gettimeoffset,
49};
50
51
52/*
53 * IQ80321 I/O.
54 */
55static struct map_desc iq80321_io_desc[] __initdata = {
56 { /* on-board devices */
57 .virtual = IQ80321_UART,
58 .pfn = __phys_to_pfn(IQ80321_UART),
59 .length = 0x00100000,
60 .type = MT_DEVICE,
61 },
62};
63
64void __init iq80321_map_io(void)
65{
66 iop3xx_map_io();
67 iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
68}
69
70
71/*
72 * IQ80321 PCI.
73 */
74static inline int __init
75iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
76{
77 int irq;
78
79 if ((slot == 2 || slot == 6) && pin == 1) {
80 /* PCI-X Slot INTA */
81 irq = IRQ_IOP321_XINT2;
82 } else if ((slot == 2 || slot == 6) && pin == 2) {
83 /* PCI-X Slot INTA */
84 irq = IRQ_IOP321_XINT3;
85 } else if ((slot == 2 || slot == 6) && pin == 3) {
86 /* PCI-X Slot INTA */
87 irq = IRQ_IOP321_XINT0;
88 } else if ((slot == 2 || slot == 6) && pin == 4) {
89 /* PCI-X Slot INTA */
90 irq = IRQ_IOP321_XINT1;
91 } else if (slot == 4 || slot == 8) {
92 /* Gig-E */
93 irq = IRQ_IOP321_XINT0;
94 } else {
95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
96 "device PCI:%d:%d:%d\n", dev->bus->number,
97 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
98 irq = -1;
99 }
100
101 return irq;
102}
103
104static struct hw_pci iq80321_pci __initdata = {
105 .swizzle = pci_std_swizzle,
106 .nr_controllers = 1,
107 .setup = iop3xx_pci_setup,
108 .preinit = iop3xx_pci_preinit,
109 .scan = iop3xx_pci_scan_bus,
110 .map_irq = iq80321_pci_map_irq,
111};
112
113static int __init iq80321_pci_init(void)
114{
115 if (machine_is_iq80321())
116 pci_common_init(&iq80321_pci);
117
118 return 0;
119}
120
121subsys_initcall(iq80321_pci_init);
122
123
124/*
125 * IQ80321 machine initialisation.
126 */
127static struct physmap_flash_data iq80321_flash_data = {
128 .width = 1,
129};
130
131static struct resource iq80321_flash_resource = {
132 .start = 0xf0000000,
133 .end = 0xf07fffff,
134 .flags = IORESOURCE_MEM,
135};
136
137static struct platform_device iq80321_flash_device = {
138 .name = "physmap-flash",
139 .id = 0,
140 .dev = {
141 .platform_data = &iq80321_flash_data,
142 },
143 .num_resources = 1,
144 .resource = &iq80321_flash_resource,
145};
146
147static struct plat_serial8250_port iq80321_serial_port[] = {
148 {
149 .mapbase = IQ80321_UART,
150 .membase = (char *)IQ80321_UART,
151 .irq = IRQ_IOP321_XINT1,
152 .flags = UPF_SKIP_TEST,
153 .iotype = UPIO_MEM,
154 .regshift = 0,
155 .uartclk = 1843200,
156 },
157 { },
158};
159
160static struct resource iq80321_uart_resource = {
161 .start = IQ80321_UART,
162 .end = IQ80321_UART + 7,
163 .flags = IORESOURCE_MEM,
164};
165
166static struct platform_device iq80321_serial_device = {
167 .name = "serial8250",
168 .id = PLAT8250_DEV_PLATFORM,
169 .dev = {
170 .platform_data = iq80321_serial_port,
171 },
172 .num_resources = 1,
173 .resource = &iq80321_uart_resource,
174};
175
176static void __init iq80321_init_machine(void)
177{
178 platform_device_register(&iop3xx_i2c0_device);
179 platform_device_register(&iop3xx_i2c1_device);
180 platform_device_register(&iq80321_flash_device);
181 platform_device_register(&iq80321_serial_device);
182}
183
184MACHINE_START(IQ80321, "Intel IQ80321")
185 /* Maintainer: Intel Corp. */
186 .phys_io = IQ80321_UART,
187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
188 .boot_params = 0xa0000100,
189 .map_io = iq80321_map_io,
190 .init_irq = iop321_init_irq,
191 .timer = &iq80321_timer,
192 .init_machine = iq80321_init_machine,
193MACHINE_END
diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c
deleted file mode 100644
index 68de247a4cca..000000000000
--- a/arch/arm/mach-iop32x/setup.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop32x/setup.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/major.h>
16#include <linux/fs.h>
17#include <linux/platform_device.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21
22#include <asm/io.h>
23#include <asm/pgtable.h>
24#include <asm/page.h>
25#include <asm/mach/map.h>
26#include <asm/setup.h>
27#include <asm/system.h>
28#include <asm/memory.h>
29#include <asm/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/hardware/iop3xx.h>
34
35#define IOP321_UART_XTAL 1843200
36
37#ifdef CONFIG_ARCH_IQ80321
38#define UARTBASE IQ80321_UART
39#define IRQ_UART IRQ_IQ80321_UART
40#endif
41
42#ifdef CONFIG_ARCH_IQ31244
43#define UARTBASE IQ31244_UART
44#define IRQ_UART IRQ_IQ31244_UART
45#endif
46
47static struct uart_port iop321_serial_ports[] = {
48 {
49 .membase = (char*)(UARTBASE),
50 .mapbase = (UARTBASE),
51 .irq = IRQ_UART,
52 .flags = UPF_SKIP_TEST,
53 .iotype = UPIO_MEM,
54 .regshift = 0,
55 .uartclk = IOP321_UART_XTAL,
56 .line = 0,
57 .type = PORT_16550A,
58 .fifosize = 16
59 }
60};
61
62void __init iop32x_init(void)
63{
64 platform_device_register(&iop3xx_i2c0_device);
65 platform_device_register(&iop3xx_i2c1_device);
66 early_serial_setup(&iop321_serial_ports[0]);
67}
68
69#ifdef CONFIG_ARCH_IQ80321
70extern void iq80321_map_io(void);
71#endif
72
73#ifdef CONFIG_ARCH_IQ31244
74extern void iq31244_map_io(void);
75#endif
76
77static void __init iop3xx_timer_init(void)
78{
79 iop3xx_init_time(IOP321_TICK_RATE);
80}
81
82struct sys_timer iop321_timer = {
83 .init = iop3xx_timer_init,
84 .offset = iop3xx_gettimeoffset,
85};
86
87#if defined(CONFIG_ARCH_IQ80321)
88MACHINE_START(IQ80321, "Intel IQ80321")
89 /* Maintainer: Intel Corporation */
90 .phys_io = IQ80321_UART,
91 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
92 .map_io = iq80321_map_io,
93 .init_irq = iop321_init_irq,
94 .timer = &iop321_timer,
95 .boot_params = 0xa0000100,
96 .init_machine = iop32x_init,
97MACHINE_END
98#elif defined(CONFIG_ARCH_IQ31244)
99MACHINE_START(IQ31244, "Intel IQ31244")
100 /* Maintainer: Intel Corp. */
101 .phys_io = IQ31244_UART,
102 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
103 .map_io = iq31244_map_io,
104 .init_irq = iop321_init_irq,
105 .timer = &iop321_timer,
106 .boot_params = 0xa0000100,
107 .init_machine = iop32x_init,
108MACHINE_END
109#else
110#error No machine descriptor defined for this IOP3XX implementation
111#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 06:17:30 -0500