Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits)
  [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
  [ARM] 3855/1: Add generic time support
  [ARM] 3873/1: S3C24XX: Add irq_chip names
  [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
  [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23
  [ARM] nommu: confirms the CR_V bit in nommu mode
  [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
  [ARM] 3870/1: AT91: Start removing static memory mappings
  [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards
  [ARM] 3868/1: AT91 hardware header update
  [ARM] 3867/1: AT91 GPIO update
  [ARM] 3866/1: AT91 clock update
  [ARM] 3865/1: AT91RM9200 header updates
  [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
  [ARM] kthread: switch arch/arm/kernel/apm.c
  [ARM] Off-by-one in arch/arm/common/icst*
  [ARM] 3864/1: Refactore sharpsl_pm
  [ARM] 3863/1: Add Locomo SPI Device
  [ARM] 3847/2:  Convert LOMOMO to use struct device for GPIOs
  [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
  ...

1 files changed, 76 insertions, 0 deletions

diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
new file mode 100644
index 000000000000..69d6302f40cf
--- /dev/null
+++ b/arch/arm/mach-iop32x/irq.c
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/mach-iop32x/irq.c
+ *
+ * Generic IOP32X IRQ handling functionality
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+static u32 iop32x_mask;
+
+static inline void intctl_write(u32 val)
+{
+        iop3xx_cp6_enable();
+        asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
+        iop3xx_cp6_disable();
+}
+
+static inline void intstr_write(u32 val)
+{
+        iop3xx_cp6_enable();
+        asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
+        iop3xx_cp6_disable();
+}
+
+static void
+iop32x_irq_mask(unsigned int irq)
+{
+        iop32x_mask &= ~(1 << irq);
+        intctl_write(iop32x_mask);
+}
+
+static void
+iop32x_irq_unmask(unsigned int irq)
+{
+        iop32x_mask |= 1 << irq;
+        intctl_write(iop32x_mask);
+}
+
+struct irq_chip ext_chip = {
+        .name   = "IOP32x",
+        .ack    = iop32x_irq_mask,
+        .mask   = iop32x_irq_mask,
+        .unmask = iop32x_irq_unmask,
+};
+
+void __init iop32x_init_irq(void)
+{
+        int i;
+
+        intctl_write(0);
+        intstr_write(0);
+        if (machine_is_glantank() ||
+            machine_is_iq80321() ||
+            machine_is_iq31244() ||
+            machine_is_n2100())
+                *IOP3XX_PCIIRSR = 0x0f;
+
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_chip(i, &ext_chip);
+                set_irq_handler(i, do_level_IRQ);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+}