[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach

This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

19 files changed, 416 insertions, 0 deletions

diff --git a/arch/arm/mach-iop32x/include/mach/adma.h b/arch/arm/mach-iop32x/include/mach/adma.h
new file mode 100644
index 000000000000..5ed92037dd10
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/adma.h
@@ -0,0 +1,5 @@
+#ifndef IOP32X_ADMA_H
+#define IOP32X_ADMA_H
+#include <asm/hardware/iop3xx-adma.h>
+#endif
+
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..58b01664ffba
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+                .macro  addruart, rx
+                mov     \rx, #0xfe000000        @ physical as well as virtual
+                orr     \rx, \rx, #0x00800000   @ location of the UART
+                .endm
+
+#define UART_SHIFT      0
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-iop32x/include/mach/dma.h b/arch/arm/mach-iop32x/include/mach/dma.h
new file mode 100644
index 000000000000..f8bd817f205d
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/dma.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/dma.h
+ *
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..b02fb56bafcc
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IOP32x-based platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/iop32x.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro get_irqnr_preamble, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+        mrc     p15, 0, \tmp, c15, c1, 0
+        mov     \tmp, \tmp
+        sub     pc, pc, #4                      @ cp_wait
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p6, 0, \irqstat, c8, c0, 0      @ Read IINTSRC
+        cmp     \irqstat, #0
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
+
+        .macro arch_ret_to_user, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c15, c1, 0
+        ands    \tmp2, \tmp1, #(1 << 6)
+        bicne   \tmp1, \tmp1, #(1 << 6)
+        mcrne   p15, 0, \tmp1, c15, c1, 0       @ Disable cp6 access
+        .endm
diff --git a/arch/arm/mach-iop32x/include/mach/glantank.h b/arch/arm/mach-iop32x/include/mach/glantank.h
new file mode 100644
index 000000000000..958eb91c0913
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/glantank.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/glantank.h
+ *
+ * IO-Data GLAN Tank board registers
+ */
+
+#ifndef __GLANTANK_H
+#define __GLANTANK_H
+
+#define GLANTANK_UART           0xfe800000      /* UART */
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/gpio.h b/arch/arm/mach-iop32x/include/mach/gpio.h
new file mode 100644
index 000000000000..708f4ec9db1d
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP32X_GPIO_H
+#define __ASM_ARCH_IOP32X_GPIO_H
+
+#include <asm/hardware/iop3xx-gpio.h>
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/hardware.h b/arch/arm/mach-iop32x/include/mach/hardware.h
new file mode 100644
index 000000000000..d559c4e6095a
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/hardware.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/hardware.h
+ */
+
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+
+#include <asm/types.h>
+
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000. The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses. See
+ * arch/arm/plat-iop/pci.c.
+ */
+#define pcibios_assign_all_busses() 1
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+
+#ifndef __ASSEMBLY__
+void iop32x_init_irq(void);
+#endif
+
+
+/*
+ * Generic chipset bits
+ */
+#include "iop32x.h"
+
+/*
+ * Board specific bits
+ */
+#include "glantank.h"
+#include "iq80321.h"
+#include "iq31244.h"
+#include "n2100.h"
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
new file mode 100644
index 000000000000..ce54705ba3d4
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/io.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IO_H
+#define __IO_H
+
+#include <mach/hardware.h>
+
+extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
+        unsigned int mtype);
+extern void __iop3xx_iounmap(void __iomem *addr);
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
+#define __mem_pci(a)            (a)
+
+#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
+#define __arch_iounmap(a)        __iop3xx_iounmap(a)
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/iop32x.h b/arch/arm/mach-iop32x/include/mach/iop32x.h
new file mode 100644
index 000000000000..abd9eb49f103
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/iop32x.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/iop32x.h
+ *
+ * Intel IOP32X Chip definitions
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IOP32X_H
+#define __IOP32X_H
+
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c4 + (reg))
+#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
+
+#include <asm/hardware/iop3xx.h>
+
+/* ATU Parameters
+ * set up a 1:1 bus to physical ram relationship
+ * w/ physical ram on top of pci in the memory map
+ */
+#define IOP32X_MAX_RAM_SIZE            0x40000000UL
+#define IOP3XX_MAX_RAM_SIZE            IOP32X_MAX_RAM_SIZE
+#define IOP3XX_PCI_LOWER_MEM_BA        0x80000000
+#define IOP32X_PCI_MEM_WINDOW_SIZE     0x04000000
+#define IOP3XX_PCI_MEM_WINDOW_SIZE     IOP32X_PCI_MEM_WINDOW_SIZE
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/iq31244.h b/arch/arm/mach-iop32x/include/mach/iq31244.h
new file mode 100644
index 000000000000..6b6b369e781c
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/iq31244.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/iq31244.h
+ *
+ * Intel IQ31244 evaluation board registers
+ */
+
+#ifndef __IQ31244_H
+#define __IQ31244_H
+
+#define IQ31244_UART            0xfe800000      /* UART #1 */
+#define IQ31244_7SEG_1          0xfe840000      /* 7-Segment MSB */
+#define IQ31244_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
+#define IQ31244_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
+#define IQ31244_BATT_STAT       0xfe8f0000      /* Battery Status */
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/iq80321.h b/arch/arm/mach-iop32x/include/mach/iq80321.h
new file mode 100644
index 000000000000..498819b737e7
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/iq80321.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/iq80321.h
+ *
+ * Intel IQ80321 evaluation board registers
+ */
+
+#ifndef __IQ80321_H
+#define __IQ80321_H
+
+#define IQ80321_UART            0xfe800000      /* UART #1 */
+#define IQ80321_7SEG_1          0xfe840000      /* 7-Segment MSB */
+#define IQ80321_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
+#define IQ80321_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
+#define IQ80321_BATT_STAT       0xfe8f0000      /* Battery Status */
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/irqs.h b/arch/arm/mach-iop32x/include/mach/irqs.h
new file mode 100644
index 000000000000..33573e09914c
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/irqs.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/irqs.h
+ *
+ * Author:      Rory Bolt <rorybolt@pacbell.net>
+ * Copyright:   (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IRQS_H
+#define __IRQS_H
+
+/*
+ * IOP80321 chipset interrupts
+ */
+#define IRQ_IOP32X_DMA0_EOT     0
+#define IRQ_IOP32X_DMA0_EOC     1
+#define IRQ_IOP32X_DMA1_EOT     2
+#define IRQ_IOP32X_DMA1_EOC     3
+#define IRQ_IOP32X_AA_EOT       6
+#define IRQ_IOP32X_AA_EOC       7
+#define IRQ_IOP32X_CORE_PMON    8
+#define IRQ_IOP32X_TIMER0       9
+#define IRQ_IOP32X_TIMER1       10
+#define IRQ_IOP32X_I2C_0        11
+#define IRQ_IOP32X_I2C_1        12
+#define IRQ_IOP32X_MESSAGING    13
+#define IRQ_IOP32X_ATU_BIST     14
+#define IRQ_IOP32X_PERFMON      15
+#define IRQ_IOP32X_CORE_PMU     16
+#define IRQ_IOP32X_BIU_ERR      17
+#define IRQ_IOP32X_ATU_ERR      18
+#define IRQ_IOP32X_MCU_ERR      19
+#define IRQ_IOP32X_DMA0_ERR     20
+#define IRQ_IOP32X_DMA1_ERR     21
+#define IRQ_IOP32X_AA_ERR       23
+#define IRQ_IOP32X_MSG_ERR      24
+#define IRQ_IOP32X_SSP          25
+#define IRQ_IOP32X_XINT0        27
+#define IRQ_IOP32X_XINT1        28
+#define IRQ_IOP32X_XINT2        29
+#define IRQ_IOP32X_XINT3        30
+#define IRQ_IOP32X_HPI          31
+
+#define NR_IRQS                 32
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h
new file mode 100644
index 000000000000..42cd4bf3148c
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/memory.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/memory.h
+ */
+
+#ifndef __MEMORY_H
+#define __MEMORY_H
+
+#include <mach/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0xa0000000)
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)        (__phys_to_virt(x))
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/n2100.h b/arch/arm/mach-iop32x/include/mach/n2100.h
new file mode 100644
index 000000000000..40b8a532b064
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/n2100.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/n2100.h
+ *
+ * Thecus N2100 board registers
+ */
+
+#ifndef __N2100_H
+#define __N2100_H
+
+#define N2100_UART              0xfe800000      /* UART */
+
+#define N2100_COPY_BUTTON       IOP3XX_GPIO_LINE(0)
+#define N2100_PCA9532_RESET     IOP3XX_GPIO_LINE(2)
+#define N2100_RESET_BUTTON      IOP3XX_GPIO_LINE(3)
+#define N2100_HARDWARE_RESET    IOP3XX_GPIO_LINE(4)
+#define N2100_POWER_BUTTON      IOP3XX_GPIO_LINE(5)
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
new file mode 100644
index 000000000000..20f923e54f46
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/system.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/system.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        local_irq_disable();
+
+        if (machine_is_n2100()) {
+                gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
+                gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
+                while (1)
+                        ;
+        }
+
+        *IOP3XX_PCSR = 0x30;
+
+        /* Jump into ROM at address 0 */
+        cpu_reset(0);
+}
diff --git a/arch/arm/mach-iop32x/include/mach/time.h b/arch/arm/mach-iop32x/include/mach/time.h
new file mode 100644
index 000000000000..0f28c9949623
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/time.h
@@ -0,0 +1,4 @@
+#ifndef _IOP32X_TIME_H_
+#define _IOP32X_TIME_H_
+#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/timex.h b/arch/arm/mach-iop32x/include/mach/timex.h
new file mode 100644
index 000000000000..a541afced3cb
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/timex.h
+ *
+ * IOP32x architecture timex specifications
+ */
+
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
new file mode 100644
index 000000000000..b247551b6f5a
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/uncompress.h
+ */
+
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+static volatile u8 *uart_base;
+
+#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
+
+static inline void putc(char c)
+{
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+        uart_base[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        if (machine_is_iq80321())
+                uart_base = (volatile u8 *)IQ80321_UART;
+        else if (machine_is_iq31244() || machine_is_em7210())
+                uart_base = (volatile u8 *)IQ31244_UART;
+        else
+                uart_base = (volatile u8 *)0xfe800000;
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..85ceb09d85f0
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000