diff options
author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:42:29 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:42:29 -0400 |
commit | f9dd2134374c8de6b911e2b8652c6c9622eaa658 (patch) | |
tree | c1b8f8d622941606b9e7247ab31d811ba4295011 /arch/arm/mach-iop13xx | |
parent | 4b652f0db3be891c7b76b109c3b55003b920fc96 (diff) | |
parent | 07a3b417dc3d00802bd7b4874c3e811f0b015a7d (diff) |
Merge branch 'md-raid6-accel' into ioat3.2
Conflicts:
include/linux/dmaengine.h
Diffstat (limited to 'arch/arm/mach-iop13xx')
-rw-r--r-- | arch/arm/mach-iop13xx/include/mach/adma.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-iop13xx/setup.c | 10 |
2 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h index 5722e86f2174..1cd31df8924d 100644 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ b/arch/arm/mach-iop13xx/include/mach/adma.h | |||
@@ -428,18 +428,20 @@ static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, | |||
428 | hw_desc->block_fill_data = val; | 428 | hw_desc->block_fill_data = val; |
429 | } | 429 | } |
430 | 430 | ||
431 | static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) | 431 | static inline enum sum_check_flags |
432 | iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) | ||
432 | { | 433 | { |
433 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | 434 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; |
434 | struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; | 435 | struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; |
435 | struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; | 436 | struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; |
437 | enum sum_check_flags flags; | ||
436 | 438 | ||
437 | BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); | 439 | BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); |
438 | 440 | ||
439 | if (desc_ctrl.pq_xfer_en) | 441 | flags = byte_count.zero_result_err_q << SUM_CHECK_Q; |
440 | return byte_count.zero_result_err_q; | 442 | flags |= byte_count.zero_result_err << SUM_CHECK_P; |
441 | else | 443 | |
442 | return byte_count.zero_result_err; | 444 | return flags; |
443 | } | 445 | } |
444 | 446 | ||
445 | static inline void iop_chan_append(struct iop_adma_chan *chan) | 447 | static inline void iop_chan_append(struct iop_adma_chan *chan) |
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index bee42c609df6..faaef95342b6 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c | |||
@@ -478,7 +478,7 @@ void __init iop13xx_platform_init(void) | |||
478 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | 478 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); |
479 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | 479 | dma_cap_set(DMA_XOR, plat_data->cap_mask); |
480 | dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); | 480 | dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); |
481 | dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); | 481 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
482 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); | 482 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); |
483 | dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); | 483 | dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); |
484 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); | 484 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
@@ -490,7 +490,7 @@ void __init iop13xx_platform_init(void) | |||
490 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | 490 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); |
491 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | 491 | dma_cap_set(DMA_XOR, plat_data->cap_mask); |
492 | dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); | 492 | dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); |
493 | dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); | 493 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
494 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); | 494 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); |
495 | dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); | 495 | dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); |
496 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); | 496 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
@@ -502,13 +502,13 @@ void __init iop13xx_platform_init(void) | |||
502 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | 502 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); |
503 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | 503 | dma_cap_set(DMA_XOR, plat_data->cap_mask); |
504 | dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); | 504 | dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); |
505 | dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); | 505 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
506 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); | 506 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); |
507 | dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); | 507 | dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); |
508 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); | 508 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
509 | dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask); | 509 | dma_cap_set(DMA_PQ, plat_data->cap_mask); |
510 | dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); | 510 | dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); |
511 | dma_cap_set(DMA_PQ_ZERO_SUM, plat_data->cap_mask); | 511 | dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); |
512 | break; | 512 | break; |
513 | } | 513 | } |
514 | } | 514 | } |