diff options
author | Dan Williams <dan.j.williams@intel.com> | 2007-02-13 11:13:04 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-17 10:04:53 -0500 |
commit | 4434c5c7fd61c6713de882a2272b66f32fe7cac3 (patch) | |
tree | f20c9c4eba18dd915f07185cee5ededf33e28c02 /arch/arm/mach-iop13xx | |
parent | f80dff9da07d81da16e3b842118d47b9febf9c01 (diff) |
[ARM] 4186/1: iop: remove cp6_enable/disable routines
This functionality is replaced by cp6_trap
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop13xx')
-rw-r--r-- | arch/arm/mach-iop13xx/irq.c | 19 | ||||
-rw-r--r-- | arch/arm/mach-iop13xx/time.c | 10 |
2 files changed, 0 insertions, 29 deletions
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index 162b93214965..b2eb0b961031 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c | |||
@@ -161,65 +161,49 @@ static void write_intsize(u32 val) | |||
161 | static void | 161 | static void |
162 | iop13xx_irq_mask0 (unsigned int irq) | 162 | iop13xx_irq_mask0 (unsigned int irq) |
163 | { | 163 | { |
164 | u32 cp_flags = iop13xx_cp6_save(); | ||
165 | write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); | 164 | write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); |
166 | iop13xx_cp6_restore(cp_flags); | ||
167 | } | 165 | } |
168 | 166 | ||
169 | static void | 167 | static void |
170 | iop13xx_irq_mask1 (unsigned int irq) | 168 | iop13xx_irq_mask1 (unsigned int irq) |
171 | { | 169 | { |
172 | u32 cp_flags = iop13xx_cp6_save(); | ||
173 | write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); | 170 | write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); |
174 | iop13xx_cp6_restore(cp_flags); | ||
175 | } | 171 | } |
176 | 172 | ||
177 | static void | 173 | static void |
178 | iop13xx_irq_mask2 (unsigned int irq) | 174 | iop13xx_irq_mask2 (unsigned int irq) |
179 | { | 175 | { |
180 | u32 cp_flags = iop13xx_cp6_save(); | ||
181 | write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); | 176 | write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); |
182 | iop13xx_cp6_restore(cp_flags); | ||
183 | } | 177 | } |
184 | 178 | ||
185 | static void | 179 | static void |
186 | iop13xx_irq_mask3 (unsigned int irq) | 180 | iop13xx_irq_mask3 (unsigned int irq) |
187 | { | 181 | { |
188 | u32 cp_flags = iop13xx_cp6_save(); | ||
189 | write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); | 182 | write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); |
190 | iop13xx_cp6_restore(cp_flags); | ||
191 | } | 183 | } |
192 | 184 | ||
193 | static void | 185 | static void |
194 | iop13xx_irq_unmask0(unsigned int irq) | 186 | iop13xx_irq_unmask0(unsigned int irq) |
195 | { | 187 | { |
196 | u32 cp_flags = iop13xx_cp6_save(); | ||
197 | write_intctl_0(read_intctl_0() | (1 << (irq - 0))); | 188 | write_intctl_0(read_intctl_0() | (1 << (irq - 0))); |
198 | iop13xx_cp6_restore(cp_flags); | ||
199 | } | 189 | } |
200 | 190 | ||
201 | static void | 191 | static void |
202 | iop13xx_irq_unmask1(unsigned int irq) | 192 | iop13xx_irq_unmask1(unsigned int irq) |
203 | { | 193 | { |
204 | u32 cp_flags = iop13xx_cp6_save(); | ||
205 | write_intctl_1(read_intctl_1() | (1 << (irq - 32))); | 194 | write_intctl_1(read_intctl_1() | (1 << (irq - 32))); |
206 | iop13xx_cp6_restore(cp_flags); | ||
207 | } | 195 | } |
208 | 196 | ||
209 | static void | 197 | static void |
210 | iop13xx_irq_unmask2(unsigned int irq) | 198 | iop13xx_irq_unmask2(unsigned int irq) |
211 | { | 199 | { |
212 | u32 cp_flags = iop13xx_cp6_save(); | ||
213 | write_intctl_2(read_intctl_2() | (1 << (irq - 64))); | 200 | write_intctl_2(read_intctl_2() | (1 << (irq - 64))); |
214 | iop13xx_cp6_restore(cp_flags); | ||
215 | } | 201 | } |
216 | 202 | ||
217 | static void | 203 | static void |
218 | iop13xx_irq_unmask3(unsigned int irq) | 204 | iop13xx_irq_unmask3(unsigned int irq) |
219 | { | 205 | { |
220 | u32 cp_flags = iop13xx_cp6_save(); | ||
221 | write_intctl_3(read_intctl_3() | (1 << (irq - 96))); | 206 | write_intctl_3(read_intctl_3() | (1 << (irq - 96))); |
222 | iop13xx_cp6_restore(cp_flags); | ||
223 | } | 207 | } |
224 | 208 | ||
225 | static struct irq_chip iop13xx_irqchip1 = { | 209 | static struct irq_chip iop13xx_irqchip1 = { |
@@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void) | |||
256 | { | 240 | { |
257 | unsigned int i; | 241 | unsigned int i; |
258 | 242 | ||
259 | u32 cp_flags = iop13xx_cp6_save(); | ||
260 | iop_init_cp6_handler(); | 243 | iop_init_cp6_handler(); |
261 | 244 | ||
262 | /* disable all interrupts */ | 245 | /* disable all interrupts */ |
@@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void) | |||
288 | set_irq_handler(i, handle_level_irq); | 271 | set_irq_handler(i, handle_level_irq); |
289 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 272 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
290 | } | 273 | } |
291 | |||
292 | iop13xx_cp6_restore(cp_flags); | ||
293 | } | 274 | } |
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c index 8b21365f653f..fc9d9d9a8429 100644 --- a/arch/arm/mach-iop13xx/time.c +++ b/arch/arm/mach-iop13xx/time.c | |||
@@ -38,11 +38,8 @@ static inline u32 read_tcr1(void) | |||
38 | unsigned long iop13xx_gettimeoffset(void) | 38 | unsigned long iop13xx_gettimeoffset(void) |
39 | { | 39 | { |
40 | unsigned long offset; | 40 | unsigned long offset; |
41 | u32 cp_flags; | ||
42 | 41 | ||
43 | cp_flags = iop13xx_cp6_save(); | ||
44 | offset = next_jiffy_time - read_tcr1(); | 42 | offset = next_jiffy_time - read_tcr1(); |
45 | iop13xx_cp6_restore(cp_flags); | ||
46 | 43 | ||
47 | return offset / ticks_per_usec; | 44 | return offset / ticks_per_usec; |
48 | } | 45 | } |
@@ -50,8 +47,6 @@ unsigned long iop13xx_gettimeoffset(void) | |||
50 | static irqreturn_t | 47 | static irqreturn_t |
51 | iop13xx_timer_interrupt(int irq, void *dev_id) | 48 | iop13xx_timer_interrupt(int irq, void *dev_id) |
52 | { | 49 | { |
53 | u32 cp_flags = iop13xx_cp6_save(); | ||
54 | |||
55 | write_seqlock(&xtime_lock); | 50 | write_seqlock(&xtime_lock); |
56 | 51 | ||
57 | asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1)); | 52 | asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1)); |
@@ -64,8 +59,6 @@ iop13xx_timer_interrupt(int irq, void *dev_id) | |||
64 | 59 | ||
65 | write_sequnlock(&xtime_lock); | 60 | write_sequnlock(&xtime_lock); |
66 | 61 | ||
67 | iop13xx_cp6_restore(cp_flags); | ||
68 | |||
69 | return IRQ_HANDLED; | 62 | return IRQ_HANDLED; |
70 | } | 63 | } |
71 | 64 | ||
@@ -78,7 +71,6 @@ static struct irqaction iop13xx_timer_irq = { | |||
78 | void __init iop13xx_init_time(unsigned long tick_rate) | 71 | void __init iop13xx_init_time(unsigned long tick_rate) |
79 | { | 72 | { |
80 | u32 timer_ctl; | 73 | u32 timer_ctl; |
81 | u32 cp_flags; | ||
82 | 74 | ||
83 | ticks_per_jiffy = (tick_rate + HZ/2) / HZ; | 75 | ticks_per_jiffy = (tick_rate + HZ/2) / HZ; |
84 | ticks_per_usec = tick_rate / 1000000; | 76 | ticks_per_usec = tick_rate / 1000000; |
@@ -91,12 +83,10 @@ void __init iop13xx_init_time(unsigned long tick_rate) | |||
91 | * We use timer 0 for our timer interrupt, and timer 1 as | 83 | * We use timer 0 for our timer interrupt, and timer 1 as |
92 | * monotonic counter for tracking missed jiffies. | 84 | * monotonic counter for tracking missed jiffies. |
93 | */ | 85 | */ |
94 | cp_flags = iop13xx_cp6_save(); | ||
95 | asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1)); | 86 | asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1)); |
96 | asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl)); | 87 | asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl)); |
97 | asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff)); | 88 | asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff)); |
98 | asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl)); | 89 | asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl)); |
99 | iop13xx_cp6_restore(cp_flags); | ||
100 | 90 | ||
101 | setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq); | 91 | setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq); |
102 | } | 92 | } |