[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files

WARNING: arch/arm/mach-iop13xx/built-in.o - Section mismatch: reference to
.init.text:iop13xx_pcie_map_irq from .text between 'iop13xx_pci_setup' (at
offset 0x7fc) and 'iop13xx_map_pci_memory'

While fixing this warning I also recalled Adrian Bunk's recommendation to
not use inline in .c files, as 'iop13xx_map_pci_memory' is needlessly
inlined.

Removing 'inline' uncovered some dead code so that is cleaned up as well.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

3 files changed, 21 insertions, 57 deletions

diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 5791addd436b..69f07b25b3c9 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -30,77 +30,65 @@
 
 /* INTCTL0 CP6 R0 Page 4
  */
-static inline u32 read_intctl_0(void)
+static u32 read_intctl_0(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
         return val;
 }
-static inline void write_intctl_0(u32 val)
+static void write_intctl_0(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
 }
 
 /* INTCTL1 CP6 R1 Page 4
  */
-static inline u32 read_intctl_1(void)
+static u32 read_intctl_1(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
         return val;
 }
-static inline void write_intctl_1(u32 val)
+static void write_intctl_1(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
 }
 
 /* INTCTL2 CP6 R2 Page 4
  */
-static inline u32 read_intctl_2(void)
+static u32 read_intctl_2(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
         return val;
 }
-static inline void write_intctl_2(u32 val)
+static void write_intctl_2(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
 }
 
 /* INTCTL3 CP6 R3 Page 4
  */
-static inline u32 read_intctl_3(void)
+static u32 read_intctl_3(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
         return val;
 }
-static inline void write_intctl_3(u32 val)
+static void write_intctl_3(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
 }
 
 /* INTSTR0 CP6 R0 Page 5
  */
-static inline u32 read_intstr_0(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
-        return val;
-}
-static inline void write_intstr_0(u32 val)
+static void write_intstr_0(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
 }
 
 /* INTSTR1 CP6 R1 Page 5
  */
-static inline u32 read_intstr_1(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
-        return val;
-}
 static void write_intstr_1(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@@ -108,12 +96,6 @@ static void write_intstr_1(u32 val)
 
 /* INTSTR2 CP6 R2 Page 5
  */
-static inline u32 read_intstr_2(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
-        return val;
-}
 static void write_intstr_2(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@@ -121,12 +103,6 @@ static void write_intstr_2(u32 val)
 
 /* INTSTR3 CP6 R3 Page 5
  */
-static inline u32 read_intstr_3(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
-        return val;
-}
 static void write_intstr_3(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@@ -134,12 +110,6 @@ static void write_intstr_3(u32 val)
 
 /* INTBASE CP6 R0 Page 2
  */
-static inline u32 read_intbase(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
-        return val;
-}
 static void write_intbase(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@@ -147,12 +117,6 @@ static void write_intbase(u32 val)
 
 /* INTSIZE CP6 R2 Page 2
  */
-static inline u32 read_intsize(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
-        return val;
-}
 static void write_intsize(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 062d2acdd5e5..63ef1124ca5c 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
 
 /* IMIPR0 CP6 R8 Page 1
  */
-static inline u32 read_imipr_0(void)
+static u32 read_imipr_0(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
         return val;
 }
-static inline void write_imipr_0(u32 val)
+static void write_imipr_0(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
 }
 
 /* IMIPR1 CP6 R9 Page 1
  */
-static inline u32 read_imipr_1(void)
+static u32 read_imipr_1(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
         return val;
 }
-static inline void write_imipr_1(u32 val)
+static void write_imipr_1(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
 }
 
 /* IMIPR2 CP6 R10 Page 1
  */
-static inline u32 read_imipr_2(void)
+static u32 read_imipr_2(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
         return val;
 }
-static inline void write_imipr_2(u32 val)
+static void write_imipr_2(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
 }
 
 /* IMIPR3 CP6 R11 Page 1
  */
-static inline u32 read_imipr_3(void)
+static u32 read_imipr_3(void)
 {
         u32 val;
         asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
         return val;
 }
-static inline void write_imipr_3(u32 val)
+static void write_imipr_3(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
 }
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 1c9e94c38b7e..69e8953832fd 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -144,7 +144,7 @@ void iop13xx_map_pci_memory(void)
         }
 }
 
-static inline int iop13xx_atu_function(int atu)
+static int iop13xx_atu_function(int atu)
 {
         int func = 0;
         /* the function number depends on the value of the
@@ -259,7 +259,7 @@ static int iop13xx_atux_pci_status(int clear)
  * data.  Note that the data dependency on %0 encourages an abort
  * to be detected before we return.
  */
-static inline u32 iop13xx_atux_read(unsigned long addr)
+static u32 iop13xx_atux_read(unsigned long addr)
 {
         u32 val;
 
@@ -387,7 +387,7 @@ static int iop13xx_atue_pci_status(int clear)
         return err;
 }
 
-static inline int __init
+static int
 iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
 {
         WARN_ON(idsel != 0);
@@ -401,7 +401,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
         }
 }
 
-static inline u32 iop13xx_atue_read(unsigned long addr)
+static u32 iop13xx_atue_read(unsigned long addr)
 {
         u32 val;