diff options
author | Dan Williams <dan.j.williams@intel.com> | 2007-04-29 04:31:51 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-04-30 10:24:50 -0400 |
commit | 7dcad376e85b6eff56f29ee21e10e1fe855f1ed7 (patch) | |
tree | f8934388ee4dbe3bd24cc674089e4d5593c94ab6 /arch/arm/mach-iop13xx/pci.c | |
parent | 8903fcce9b91bab6bb98adbb57a4edfc372c8bff (diff) |
[ARM] 4341/1: iop13xx: fix i/o address translation
PCI devices were being programmed with an incorrect base address value.
This patch moves I/O space into a 16-bit addressable region and corrects
the i/o offset.
Much thanks to Martin Michlmayr for tracking this issue and testing
debug patches.
Cc: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop13xx/pci.c')
-rw-r--r-- | arch/arm/mach-iop13xx/pci.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 89ec70ea3187..d907a2aadfe6 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c | |||
@@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
1023 | << IOP13XX_ATUX_PCIXSR_FUNC_NUM; | 1023 | << IOP13XX_ATUX_PCIXSR_FUNC_NUM; |
1024 | __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); | 1024 | __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); |
1025 | 1025 | ||
1026 | res[0].start = IOP13XX_PCIX_LOWER_IO_PA; | 1026 | res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; |
1027 | res[0].end = IOP13XX_PCIX_UPPER_IO_PA; | 1027 | res[0].end = IOP13XX_PCIX_UPPER_IO_PA; |
1028 | res[0].name = "IQ81340 ATUX PCI I/O Space"; | 1028 | res[0].name = "IQ81340 ATUX PCI I/O Space"; |
1029 | res[0].flags = IORESOURCE_IO; | 1029 | res[0].flags = IORESOURCE_IO; |
@@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
1033 | res[1].name = "IQ81340 ATUX PCI Memory Space"; | 1033 | res[1].name = "IQ81340 ATUX PCI Memory Space"; |
1034 | res[1].flags = IORESOURCE_MEM; | 1034 | res[1].flags = IORESOURCE_MEM; |
1035 | sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; | 1035 | sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; |
1036 | sys->io_offset = IOP13XX_PCIX_IO_OFFSET; | 1036 | sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; |
1037 | break; | 1037 | break; |
1038 | case IOP13XX_INIT_ATU_ATUE: | 1038 | case IOP13XX_INIT_ATU_ATUE: |
1039 | /* Note: the function number field in the PCSR is ro */ | 1039 | /* Note: the function number field in the PCSR is ro */ |
@@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
1044 | 1044 | ||
1045 | __raw_writel(pcsr, IOP13XX_ATUE_PCSR); | 1045 | __raw_writel(pcsr, IOP13XX_ATUE_PCSR); |
1046 | 1046 | ||
1047 | res[0].start = IOP13XX_PCIE_LOWER_IO_PA; | 1047 | res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; |
1048 | res[0].end = IOP13XX_PCIE_UPPER_IO_PA; | 1048 | res[0].end = IOP13XX_PCIE_UPPER_IO_PA; |
1049 | res[0].name = "IQ81340 ATUE PCI I/O Space"; | 1049 | res[0].name = "IQ81340 ATUE PCI I/O Space"; |
1050 | res[0].flags = IORESOURCE_IO; | 1050 | res[0].flags = IORESOURCE_IO; |
@@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
1054 | res[1].name = "IQ81340 ATUE PCI Memory Space"; | 1054 | res[1].name = "IQ81340 ATUE PCI Memory Space"; |
1055 | res[1].flags = IORESOURCE_MEM; | 1055 | res[1].flags = IORESOURCE_MEM; |
1056 | sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; | 1056 | sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; |
1057 | sys->io_offset = IOP13XX_PCIE_IO_OFFSET; | 1057 | sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; |
1058 | sys->map_irq = iop13xx_pcie_map_irq; | 1058 | sys->map_irq = iop13xx_pcie_map_irq; |
1059 | break; | 1059 | break; |
1060 | default: | 1060 | default: |