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authorLinus Walleij <linus.walleij@linaro.org>2011-09-06 03:08:13 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-09-06 19:47:26 -0400
commitbb9ea77846620ed2b37e74c852d72c7a476b248c (patch)
treeeca9a3b9ff38e26ac3436f813338190c3f54ccf5 /arch/arm/mach-integrator
parent1df726ef0a700587a712a3660b2caa8e533c7de9 (diff)
ARM: 7081/1: mach-integrator: fix the clocksource
I was intrigued by the fact that the clock stood still on the Integrator, but it wasn't strange at all, because the timer was set up all wrong and probably has been for a while. With this patch the clock starts ticking again: make the timer periodic (reload), |= on the divisor bit and load the timer before starting it. Cc: stable@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-integrator')
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2fbbdd5eac35..fcf0ae95651f 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -337,15 +337,15 @@ static unsigned long timer_reload;
337static void integrator_clocksource_init(u32 khz) 337static void integrator_clocksource_init(u32 khz)
338{ 338{
339 void __iomem *base = (void __iomem *)TIMER2_VA_BASE; 339 void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
340 u32 ctrl = TIMER_CTRL_ENABLE; 340 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
341 341
342 if (khz >= 1500) { 342 if (khz >= 1500) {
343 khz /= 16; 343 khz /= 16;
344 ctrl = TIMER_CTRL_DIV16; 344 ctrl |= TIMER_CTRL_DIV16;
345 } 345 }
346 346
347 writel(ctrl, base + TIMER_CTRL);
348 writel(0xffff, base + TIMER_LOAD); 347 writel(0xffff, base + TIMER_LOAD);
348 writel(ctrl, base + TIMER_CTRL);
349 349
350 clocksource_mmio_init(base + TIMER_VALUE, "timer2", 350 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
351 khz * 1000, 200, 16, clocksource_mmio_readl_down); 351 khz * 1000, 200, 16, clocksource_mmio_readl_down);