ARM: i.MX5: Add PATA and SRTC clocks

This adds the clock gates and the binding documentation
for PATA and SRTC.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a163e0e365dc..efbccc0dcada 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -110,6 +110,7 @@ enum imx5_clks {
         owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
         cko1_sel, cko1_podf, cko1,
         cko2_sel, cko2_podf, cko2,
+        srtc_gate, pata_gate,
         clk_max
 };
 
@@ -266,6 +267,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
         clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
         clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
+        clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
+        clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))